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BQ40Z50-R2: Discharge control when COV

Part Number: BQ40Z50-R2

Hi All:

The application I am using the BQ40Z50-R2 on disables both the charge and discharge when COV is reached.  I am looking only to disable the charge side and similarly only disable the discharge when CUV is reached.  I believe this is possible but can't find the configuration settings that will allow for this.

  • Hello Joe,

    Let me check if there is a configuration to allow this and get back to you.

    Sincerely,

    Wyatt Keller

  • Thanks Wyatt:

    It is a bit odd the behavior in I see on BQ Studio the COV flag set but XCHG and XDCG seem to stay green. 

    when Operation status goes from 0x0187 to  0x4983 XCHG and CHG seem to be correct but I still get disabling of discharge.  Very odd.

  • Hello Joe,

    Does this occur on all your boards? Can you try it on a different EVM?

    Could you get a scope grab of the DSG FET operation? 

    Sincerely,

    Wyatt Keller

  • Hi Wyatt:

    After a bit of a holiday, I have checked the MOSFET gate voltages.  During normal operation both the charge and discharge gate voltages are 27V.  Near full charge the charge voltage drops to 13.5 V ( I will try to get a scope trend) while discharge remains unchanged.  After reaching COV both driver voltages go to zero.  The key status bits are as follows

    COV - High

    SS - High

    XCHG - High

    XDSG - Low

    Even though XDSG is low discharge is disabled.  Once enough current is drained to allow Recover to trigger, then the system is back to normal.  
    My thinking is that the SS status is disabling discharge.  I can't find a setting that regulates triggering protections so that I can separate discharge and charge. 

    One option I am considering is that the method of using the BMS protection as a charge control method might be not ideal and I could simply set the charger voltage down to below the protection point and it should resolve this problem as the protection would not be encountered.  This seems sub-optimal.

    I will check the behavior on CUV also and see if it has an issue on the low side also.

  • Hello Joe,

    Is this on multiple boards or just your test setup with an EVM? Could you send me your .gg file and log files of this occurring? Is FET_EN active? if you have manual control the FW won't be triggering the gates.

    Sincerely,

    Wyatt Keller

  • HI Wyatt:

    I think you might be on the right track with the FET control.  I will post the gg and an xls version of the log file.

    Aging Test 1.xlsx20200602.gg.csv