Hello E2E,
In section 9.1.2 of the TPS22967 DS, it states that:
Because of the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN dip caused by inrush currents during start-up; however, a 10-to-1 ratio for capacitance is not required for proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VIN dip upon turnon due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise time (see below).
In my customer's application, they are using 47uF of Cin and 22uF of Cout = Cl. However, there is an additional 100uF + 47uF of Cout at an FPGA input. How critical is the Cin > Cout spec. If there is some distance between the output of the load switch and the FPGA, would that help mitigate the need for more Cin? Are there concerns about the Cin node have 22uF and Cout have 169uF?
Thanks!
Russell
