UCC21750: Troubleshoot why FLT pin is low

Forgot to mention, there is no MOSFET connected to the board at the moment.

Hi,

FLT should only be pulling low if there is DESAT on your switch, after the deglitch filter, and when PWM input is HIGH, so its strange that it should be triggering when the devices aren't operating. We might also look at a cause on primary side as well.

Would you be able to share your schematic for your design?

And , could you try toggling RST according to D/S in order to clear the FLT condition, and let us know about the behavior after that point?

Best

Dimitri

Would you be able to share your schematic for your design?

Here is the schematic for the gate drive portion.

Buffer part is here. Not pictured is the 10k pull up resistor for each FLT1-FLT6 line. Also, I failed to mention last time, the FLT1-FLT6 signals are also connected to GPIO on a uC. The GPIOs on the uC are set to "no pull".

And , could you try toggling RST according to D/S in order to clear the FLT condition, and let us know about the behavior after that point?

I tried this, nothing happened. In fact, here is the weird part. When I first power on and EN is low, all FLT pins are high as expected. When turn EN to high, the FLT pins go low. After that, even if I toggle the EN multiple times as suggested by the datasheet, the FLT pins remain low.

Another strange thing is, when I lift pin 1 on the buffer IC to remove the buffer 1A from the circuit, the FLT1 behaves as expected - it remains high at all times. So it seems the buffer has some effect, but it doesn't make any sense.

A note, the UCC21750 used on the board has the P21750 note on the IC, I'm pretty sure it is a preproduction part as we ordered this sometime in May or June 2019.

Yes that is really strange.

So just to confirm, you're having issues with ALL fault pins.

When you probe FLT1 through FLTN, they are ALL low (these are the inputs to your buffer)

But, when you lifted pin 1 on the buffer, FLT1 went high, which is correct operation (again, input-side of buffer). Is this correct?

If this is the case, can you try to desolder the buffer IC from your PCB completely and check FLT1->FLTN levels before and after removal?

Best

Dimitri

Yes, your description is correct on what I am seeing. I agree, I have considered desoldering the buffer, or maybe lifting all of the buffer input pins.

If the UCC21750 is a preproduction version, could this have an impact?

Got it, thanks for confirming.
UCC21750 is not a preproduction version at all, and this issue is very strange which we haven't encountered before.

based on your description It is almost sounds like the buffer itself is shorting inputs to ground, which itself seems very unlikely. i couldn't see any issues with your schematic either.

Lifting the buffer on outputs can't cause the device itself to unlatch a clear fault, so its safe to say it is relating to the buffer or something else on primary side that causes the outputs to pull low, but the gate driver IC should still have no actual fault latched.

The only other mechanism  i could think of is if, when connecting the buffer, buffer it is shorted internally so consumes so much current it causes the 3.3V rail to drop out, but this would be easy to check and seems increibly unlikely, and it still wouldn't explain why lifting one input pin caused the FLT to go back high

If possible, lets try by removing power to the buffer by cutting VCC or GND, then (or lifting input pins ) on your hex buffer and see if that caused the rest of FLT pins to function OK, then we could isolate the point of the issue.

Best

Dimitri

Hi, 

I went ahead and desoldered the entire buffer chip and lifted the GPIO pins from the uC (microcontroller) that are inputs for the FLT1-FLT6 signals. So now the FLT signal is only influenced by the UCC21750.

No matter what I try, the FLT signal still goes low when the uC commands the EN to high. I tried giving PWM inputs to the IN+ pin and it doesn't make any difference.

Here is a picture of the chip on the PCB. Can you tell from the markings if this is the correct part?

Hi,

This is the right IC.

FLT can only go LOW when PWM input is HIGH, and can be reset if nRST goes low longer than the glitch filter time. If FLT goes low even when PWM inputs start out low and stay low, there is either a problem with the board, and potentially but very unlikely, the drivers. potential problem with the board could be fabrication tolerace which leads to some insuficcient clearance in a via with ground plane for example, then its shorted internally. I've had that happen personally.

Again, your schematic looks fine. Nothing there should be causing an issue. Now we've eliminated one possibility 

Can we do some further test to determine a board problem or driver problem? Lets go step by step, and i apologize if these tests seem very simple or you've already done them. I'm not sure If you've done any of these debug steps! Do you know if your VIA clearance around a copper pour is low?

1. Disconnect all supplies and inputs, Check resistance / continuity with DMM from nFLT node (at the resistor R10) to digital ground. What is the result?
2. Select Left driver, Lift pin 13 (nFLT), Repeat the Contuinty/Res check to D_GND. What is the result?
   
   1. If No continuity, power on and ensure PWM inputs low, is nFlt measured at the resistor still low? Voltage at DESAT pin also low?
3. Put Left driver pin back to Pad, Repeat Step2 with Right Driver by lifting its nFlt pin

Best

Dimitri

Okay, I didn't exactly do the things you just mentioned but I have a new finding.

When I made the first post with the table of values, I guess I didn't measure everything very thoroughly. I realized that because of a firmware bug, I was actually sending a '1' for the bottom PWM. I changed the firmware to send all '0' and now the FLT line is high as expected. However, it still doesn't totally explain why there was the FLT in the first place. Do the PWMs need to be low first when I set EN to high?

Thats good. Now is normal operation?

user5151666 said:

Do the PWMs need to be low first when I set EN to high?

They Don't necessarily need to be, but i think you'd want to start the cycle when EN is enabled. If EN is low and theres input, there should not be a way to trigger FAULT

best

dimitri

By disconnecting the FLT lines from the uC and buffer, I tracked the issue down to the root. Without a MOSFET connected, the desat pin voltage charges up. If the PWM duty cycle is long enough the voltage will go past the threshold, yellow trace is the desat pin voltage.

Initially when I measured 200mV on the desat pins, it was most likely that the UCC21750 had already tripped and disabled the outputs, but there was likely a big initial spike on the desat pin to trip it. When I connect a MOSFET, things behave as expected.

Okay, thanks for the help. It is always good to have someone I can bounce things off of.