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UCC28950: Tmin configuration considerations

Kaji@PAN
Mastermind 7830 points
Part Number: UCC28950
Other Parts Discussed in Thread: UCC21520

Hi,

I previously asked about the FET breaking when the thread below gets under load.
I'm still looking into setting Tmin.
So I would like to ask you a question about Tmin.

I initially set Tmin to 160ns.
First, it is known that there is a variation of Tmin of 20%, so the minimum is 128 ns.

(question 1)
I ask about the timing of OUTx output, because longer Tmin setting eliminates FET damage.
Regarding OUTA/B and OUTD/C of UCC28950, is the logic control to ensure that OUTD falls after OUTA rises?
I am worried that the logic timing will not be inverted between OUTA and OUTD.
In the block diagram of the data sheet, the content is a black box.

(Question 2)
There is ΔTadbc in the electrical characteristics of the data sheet. min-50ns, max50ns.
What kind of timing does this show?
Does it affect the setting of Tmin?

(Question 3)
UCC25210 is used as the gate driver of UCC28950. One for OUTA/B, one for OUTD/C.
Looking at the UCC25210 data sheet, the delay of two UCC25210 from Tpdhl and Tpdlh is as follows.
30ns(max)-14ns(min)=16ns
In the setting of Tmin, I think that it is necessary to consider this delay between OUTA/B and OUTD/C. Is my opinion correct?

(Question 4)
Are there other items to consider in the setting of Tmin other than the above?

Best regards,

  • 0
    Mastermind 7830 points
    The gate driver for UCC28950 was UCC21520.
  • 0 in reply to Kaji@PAN
    TI__Mastermind 25570 points

    Hello Kaji-san

    A1/ The signal pair OUTA and OUTB are fixed, 50% duty cycle signals and the OUTC/OUTD pair are phase shifted with respect to OUTA/OUTB. The logic ensures that OUTD will always fall AFTER OUTA rises. (and OUTOUTC will always fall AFTER OUTB rises). The reason for this is that OUTD is turned OFF when the PWM comparator trips. The PWM comparator trips after the CS signal reaches the trip threshold set by the error amplifier output. The current starts to flow when OUTA turns ON and stops when OUTD turns OFF. There is no possibility of an inversion of this logic.

    A2/ Tadbc parameter refers to the differences in internal propagation delays in the paths used to turn OUTC and OUTD off. This should not affect your choice of Tmin.

    A3/ Yes you are correct. The driver has really good matching between its two channels but the matching between two individual driver ICs won't be as good. This would also affect your choice of Tmin.

    A4/ The main thing to consider is that the performance of the power stage affects your choice of Tmin. Also, different Tmin choices will give you different burst mode rates and different burst lengths. All of this is practically impossible to predict in advance and the mormal approach is to built the hardware and optimise the Tmin by experiment. This is also true of the DELAB, DELCD, DELEF settings.

    Regards
    Colin