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From figure 48 of the datasheet I can see that the nFLT output is latched and PGOOD is not. Other than that, any issue that causes nFLT to be triggered is also going to cause PGOOD to be NOT driven. Am I missing something?
James
Yes, that's the figure. I don't see an time when nFLT would be triggered and PGOOD wouldn't be deactivated, or vice-versa.
HI James,
nFLT and PGOOD are two independent signals. Below are the conditions when these signals assert.
Hi James,
Does my above reply answer your query ? Do let me know if you have any other questions ?
Hi Praveen,
Thanks for the detailed response. When any of those fault conditions occur, the output FET will be turned OFF though right? If that is the case the PGOOD will be deactivated (allowed to be pulled high by external resistor) when any of these faults occur. Is that correct?
James.
Thanks again Praveen.
As I'm designing this chip into a schematic, it became obvious that I could use the PG output to sequence the power supply startup AND use the nFLT output to to go a micro-controller at a different I/O level for monitoring. I'll leave that idea for anyone who stumbles across this post.
James.