Hi,
I want to implement a priority mux with automatic failover as shown in "Basics of Power MUX" (SLVAE51–November 2018) Figure 10 (attached). The implementation uses a source follower FET to force the second priority mux into OVP when the primary voltage is present. The same diagram is also shown in "Power Multiplexing Using Load Switches and eFuses" (SLVA811A - June 2017) Figure 16.
My application warrants a higher current than the TPS26600 and so I would like to use the TPS26630. The datasheet for this part (SLVSE94E -- March 2020) even provides an implementation of a priority mux in Figure 53, but connects it differently than as the TPS2660x. In the TPS2660x, the source follower is connected to VIN2, but in the TPS2663x, the drain of the source follower is connected in between the back-to-back power FETs. The drawing has clearly gone out of its way to connect it like this, but I am not sure why it is implemented this way.
In the case of the TPS2663x, why should the SF drain be connected to the Q3 drain instead of VIN_AUX? Can it be connected to VIN_AUX instead?
