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UCC28951: How to synchronize to external clock

Part Number: UCC28951
Other Parts Discussed in Thread: UCC28950

Hello, team

A customer wants high switching frequency accuracy (+/- 0.5% or less) in UCC28950 (or UCC28951) applications and is therefore considering synchronous operation from an external clock pulse.

Is there any document that describes about how to achieve it?
I know the SLUA609 application note on synchronous operation, but if you have any other application documentation or reference designs for external clock synchronization, please introduce them.

Regards,
H.Someno

  • Hello Someno-san

    I'd encourage the customer to choose the UCC28951 device because it is an enhanced version of the UCC28950. It is a fully compatible drop-in replacement for the UCC28950. Refer to application note SLUA853 at http://www.ti.com/lit/an/slua853/slua853.pdf for more details. The UCC28951 is typically the better choice, especially for applications where the system may have to operate simultaneously at a duty cycle> 90% and current limit.

    I don't have a document describing synchronising to an external source but the SLUA609 can be used as a reference. 

    The amplitude of the SYNC signal input to a slave device should be 5V or 3.3V. The SYNC pin threshold is typically 2.25V.

    When the device is disabled, while powered on, it will actively try to pull the SYNC pin low with a 200Ω (nominal) between its output and the SYNC pin. For this reason it is a good idea to place a 1k Ω resistor in series with the SYNC signal source to prevent it being overloaded.

    The UCC295x device synchronises to the falling edge of the SYNC pulse. Normally the SYNC pulse will have a 50% duty cycle but this is not critical. The SYNC pulse should be longer than 300ns and there is some margin there too.

    Do remind the customer that if the SYNC source fails or stops the UCC2895x will run using its own internal clock. If the SYNC signal stops in the HIGH state the UCC2895x outputs will freeze. There is a high probability of power stage damage if this happens while a diagonal pair of switches are on (OUTA/OUTD or OUTB/OUTC)

    Please let me know if you need any further information.

    Regards
    Colin

  • Colin-san,

    Thanks for your reply. I would like to know about 200Ω (nominal) between its output and the SYNC pin in your comments.

    - Does “its output” in your comments  mean OUTx terminal?
    - Does “200Ω (nominal) between its output and SYNC pin” become active only when IC is disabled under powered-on?
      (In other word, except for above limited conditions, is the 200Ω inactive?)

    Regards,

    H.Someno

  • Hello Someno-san

    I'm sorry - I wasn't clear.

    The 200R pull down exists between the SYNC pin and GND pin. It is active ONLY when the IC is disabled (SS/EN pulled below the 500mV VSS_STD threshold) and powered on.

    Regards

    Colin