UCD90160A: Example file for FPGA power up sequencing as mentioned in application note slyt598

Hello

I am designing with the UCD90160A for the first time. I need an example file for the Figure 6 mentioned in application note slyt598 for the sequence of FPGA power sequence (Core Supply, Block RAM Supply, Auxillary Supply, IO supplies). Though I have seen some training videos on TI website I need this file to understand better how to define the ramp up times etc. Should Rails and Enables or Logic GPOs be used for the outputs? Please send a sample .tifsp example file.

Thanks