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UCC21750-Q1: Active pulldown function?

Zhehui Guo
Prodigy 130 points
Part Number: UCC21750-Q1
Other Parts Discussed in Thread: UCC21750

Hi,

I have a question about active pull-down function of UCC21750.

According to the datasheet, "ucc21750 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature can prevent the output be false turned on before the device is back to control."

Does the high impedance status mean pulldown capability? I am wondering whether high impedance status would effectively avoid false turning-on? What if the miller current (caused by the complementary switch's on/off transient) go through this high impedance?

Many thanks.

Bests,

Zack

  • 0
    TI__Genius 10652 points

    Zack,

    The important thing to remember is that this active pulldown basically turns on the pulldown fet  via RA, but its only valid when VDD is OPEN/floating. This is more of a last ditch measure to protect the IGBT, this is not a consideration of the normal turn-off procedure.

    During normal turn-off, the pull-down internal NMOS pulls the gate down to VEE+~2V, at which point (if connected), the miller clamp pulls the gate down in parallel.

    During normal operation, your VDD is powered, not floating, so "active pulldown" feature meantioned in datasheet is not helpful to preventing false turn-on during normal operation. Miller clamp and/or negative VEE bias are helpful to preventing false turn-on when VDD is powered.

    If this answered your questions, please let me know by pressing the green button. Otherwise, let me know if you have further questions.

    Best

    Dimitri

  • 0 in reply to dimitri james
    Prodigy 130 points

    Hi Dimitri，

    Many thanks for your quick response. I think I am more clear now.

    You mentioned "this active pulldown basically turns on the pulldown fet  via RA" I have two follow-up questions.

    Q1- Is this (in the green circle) a NMOS? I would like to double-check.

    Q2- When Vdd is open/floating, is point "a" floating or pull-down to COM by the control circuit? 

    Many thanks.

    Bests,

    Zhehui

  • 0 in reply to Zhehui Guo
    TI__Genius 10652 points

    Zhehui,

    Zhehui Guo said:
    Q1- Is this (in the green circle) a NMOS? I would like to double-check.


    Yes.

    Zhehui Guo said:
    Q2- When Vdd is open/floating, is point "a" floating or pull-down to COM by the control circuit? 

    Because the driver block is referened to VEE (required so that it could pull-down to VEE), if only VDD gets disconnected, but VEE is still powered, the voltage at that point should eventually reach to VEE. Because the circuit is not exactly powered, it could be some time and might be at an intermediate voltage at some time. But it should be close to VEE. If VEE is tied to COM, then you'll know that it will pull it to VEE which is same potential as COM. If theyre not tied together, it should be at VEE.

    If this answered your questions, please let me know by pressing the green button. Otherwise, let me know if you have further questions.

    Best

    Dimitri

  • 0 in reply to dimitri james
    Prodigy 130 points

    Hi Dimitri，

    Many thanks for your patience. Actually, I have one more follow-up question on this topic. Can I reach you to ask via e-mail? Many thanks.

    Bests,

  • 0 in reply to Zhehui Guo
    TI__Genius 10652 points

    Zhehui,
    I ask that you for a new question, you could post it on this thread or a new thread. That way its easier for us to support, and also other people with the same question can easily find the answers here.

    Best

    Dimitri