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LM5050-1: Gate drive noise immunity issue

user5105395
Prodigy 70 points
Part Number: LM5050-1

Hi：

We use LM5050 to control three low-Rdson MOSFET(60V/1.4mohm) as a Oring-Diode for 28V/100A output. A separated 10V auxiliary power to supply this IC, and OFF pin was connected to GND，

The abnormal occurred in the no-load and light load condition, we observe output voltage waveform, the output voltage drops 0.5-1V drop with uncertain time period, the drop lasts 0.5~1ms and the interval is about several ms to teens of ms, it looks like the Oring-MOS gate was disturbed by the noise, however when we measure the waveform of the gate, once the probe of the scope was touch the gate pin, the abnormal was disappeared, so we cannot confirm the output voltage's drop come from the gate driver's abnormal. 

We also use the above circuit in two DC/DC converters which was used as parallel output by droop current sharing method, while the DC/DC applied synchronous rectifier. Occasionally,  when one DC/DC converter startup as the other DC/DC keeps off, we measure the voltage before the Oring-MOS in the off converter. It looks like the LM5050 gives a wrong signal when the first DC/DC strartup,  when we measure the waveform of the output of LM5050, the abnormal was gone. Even one probe(we use differential probe to grasp the waveform)  touch on the LM5050 pin-5, LM5050 operate normally. We suspect LM5050 has weak noise immunity.

  • 0
    TI__Genius 16305 points

    Hello E2E user,

    Light load oscillation can occur when large MOSFET with low RdsON are used in parallel and this is due to linear regulation of the LM5050 controller which tries to regulate the source-drain voltage to 22mV by controlling the gate voltage.

    At nominal load, Vgs is close to 4.5V or 5V and as the current increases, Vgs also increases (reduces RdsON to maintain 22mV source-drain voltage).

    As the load decreases, Vgs is also reduced (increases RdsON to maintain 22mV source-drain voltage) but it moves closer to Vgs(th) of MOSFET.

    At very light load or no load there can be oscillation of the MOSFETs.

    This can be avoided by either adding a series combination of "resistor + ceramic capacitor" from drain to GND. Adding a 0.1uF + 10ohm combination can help to avoid oscillation at the gate pin. Another way is to add small capacitance similar to probe capacitance to the gate pin.

    Regards,
    Kari.

  • 0 in reply to Karikalan Selvaraj
    Prodigy 70 points

    Hi，Kari：

    1）Your suggestion “from drain to GND adding 0.1uF+10mohm" GND is LM5050 GND pin or output voltage return, we place a diode from LM5050-GND for 28V GND to avoid reverse voltage. Is it necessary to place a R+C from source of Oring MOSFET to GND? 

    2) We had placed a 1n or 10n capacitor between gate and source of Oring-FET, but no use. Oring-FET is not oscillation, it is assumed the gate drive lost randomly, we can seen the waveform because it is all ok after we place probe on gate. 

    3) We found another issue. When 28V voltage is very low, that means PIN-in and Pin-out voltage is very low(<5V) while external Vcc is ok, LM5050 output a drive signal and Oring-FET is completely ON! That caused problem when we parallel output. 

    GS Huang

  • 0 in reply to user5105395
    TI__Genius 16305 points

    Hello GS Huang,

    1. I was referring to add 0.1uF and 10ohm from Drain to LM5050 IC GND pin. Note that it is 10ohm and not 10mohm.

    2. If adding 10n at gate does not help, we can rely on adding the RC combination to reduce the oscillation (as in item 1).

    3. what is the voltage at IN and OUT when you see that gate voltage is always ON? Is there is reverse condition expected from OUT to IN (reverse current)?

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    TI__Genius 16305 points

    Hello GS Huang,

    Can you also share the MOSFET part number you are using for this 28V/100A deign, is it single MOSFET or more MOSFETs in parallel.

    Please share this info, because when using with two or more MOSFETs in parallel, it is recommended to have gate resistor for each of the MOSFET seperately to avoid Vgs(th) mismatch (slight) between two same MOSFETs.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    Prodigy 70 points

    Hi，Kari:

     We use three FDMT80060DC in parallel as Oring-MOSFET, place a 1ohm resistor in each gate. 

    GS Huang

  • 0 in reply to Karikalan Selvaraj
    Prodigy 70 points

    Hi, Kari:

    When IN and OUT pin voltage <5V, the gate PIN is always high. In this condition, OUT pin was ramp up by one parallel converter with the rate of several V/ms.  IN pin voltage was pull up by OUT pin. That is not our expected. 

    GS Huang

  • 0 in reply to user5105395
    TI__Genius 16305 points

    Hello GS Huang,

    To avoid the gate drive turn ON/OFF or output voltage of OR-ing having voltage drop, we have one more additional recommendation other than recommended earlier.

    Since you are using three MOSFETs in parallel, recommended add series gate resistor of about 5ohm for each of the MOSFET seperately. This can avoid MOSFET turn ON issues due to Vgs(th) mismatch between the 3 MOSFETs.

    Next, if you do not have sufficient capacitance on the output (cathode pin side), then this can cause output voltage to drop at light load. At lease sufficient amount of capacitance is required to support the minimum load condition. Electrolytic capacitor with medium value ESR (0.1ohm) would help to minimize the gate turn on/off. 

    If you Iq current is not a concern, adding a small 1mA or if possible 10mA load current could help to resolve this issue.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    TI__Genius 16305 points

    Hello GS Huang,

    Let us know if you have got a chance to look at this E2E thread reply from us.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    Prodigy 70 points

    Hi, Kari:

    Yes, I got your recommendations. Now we modify the circuit to avoid the LM5050 ON when IN and OUT pin are low. We will try to chance gate resistors later. 

    GS Huang

  • 0 in reply to user5105395
    TI__Genius 16305 points

    Hello GS Huang,

    Ok noted.

    On the next issue of Gate ON when VIN is <5V during parallel supplies in ORing with external VCC >5V, it is not expected behavior, IC is expceted to block reverse current and turn off.

    Do you see reverse current flow from one power supply to another? Based on the information provided, OR-ing of two 28V power supply rails with external VCC powering Vs pin for both.

    Are you ramping down two rails at same time from 28V to 0V?

    Because if two rails are 28V and as soon as one rail drops below 28V, other rail takes over load current, turns off the first on because of reverse current blocking.

    Could you clarify on this?

    Regards,

    Kari.