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TPS22990: IPG, LKG Test Parameter

Abe Hortillano
Prodigy 215 points
Part Number: TPS22990

Hello,

I would like to ask for technical support on my test setup for the leakage current into the PG pin of the device. 

I always get the values of around 1uA , which is already outside the guaranteed maximum IPG,LKG of the device.

Here is how I did it:

1. Supply 3.3V on VBIAS pin

2. Force  0V on VOUT pin

3. Force 3.3V on  VIN pin

4. Force 1.2V on ON pin (enable switch)

5. Then Force 5V on PG pin, and measure current

* CT and PG pins have no connection

Is this a correct and valid setup? And how is testing an output pin current leakage different from an input leakage test?

Thank you for all your help.

Regards,

Abraham

  • 0
    TI__Genius 13760 points

    Hi Abraham,

    Welcome to E2E!

    The PG pin is labelled as an output, but this is an open drain pin. When the device is ON, the FET from PG pin to GND will be OFF and the PG signal will be asserted high by the pull up resistor to a power source. Although the FET from PG pin to GND is off, there will be some leakage current to trough the pin of the TPS22990.

    As for the test, by forcing 0V on VOUT do you mean you are leaving the output floating and it has the 3.3V from the input since the switch is enabled, or are you forcing 0V on VOUT by shorting the output to GND?

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 215 points

    Hello Andy,

    Thank you for the immediate response to my query.

    1. I am confused when you said "When the device is ON, the FET from PG pin to GND will be OFF...". Do you mean that when the device is ON, the NMOS channel from the PG pin is ON, right? So that the voltage across the PG pin is always with respect to ground.

    2. I meant the forcing of 0V on VOUT as shorting the output to GND. 

    Thank you.

    Best regards,

    Abraham

  • 0 in reply to Abe Hortillano
    TI__Genius 13760 points

    Hi Abe,

    Before the device is fully powered, the NMOS FET will be ON. This will ground the PG pin and will keep it low until fully powered. Once the switch has been fully turned on, the internal NMOS from PG pin to GND will turn OFF. With the NMOS OFF the PG pin will be left floating which if configured correctly with a pull-up resistor to a power source the PG pin be asserted high by the power source.

    On the testing conditions I have concerns on VOUT being shorted to GND. The TPS22990 does not have any protective features for which a short to ground on the output could be damaging the device.

    To measure the leakage on the PG pin when the device is enabled I recommend using a pull up resistor from the 5V supply to the PG pin like it would normally be used in the system. With VIN = VBIAS = 3.3V have VOUT open, or place a load that will pull a current within the abs max specs of the device(10A). Ensure that the power supply to VIN and VBIAS is applying 3.3V to the pins of the device and not adjusting the voltage due to the power supply being current limited.

    Do the measurement on the device you're currently working on, but if possible also run the measurement on an untested device since the short to ground on the output could have potentially damaged the initial device.

    I would avoid shorting the device to ground when it is enabled to prevent any possible damage.

    Best regards,

    Andy Robles