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BQ24450 using more current than specified

Oli
Prodigy 80 points

 

I have since prototyped the evaluation board based on the BQ24450, found here http://focus.ti.com/lit/ug/sluu464/sluu464.pdf

It appears to test well for our application - the only difference between the default schematic is that we are using a P type FET with a 10K pull up. There is only one remaining outstanding issue.

If the current supplied is more than the current limit, the circuit uses the predicted < 2mA + the current drawn by R5 (we are using a 10K pull up). If however we limit the supply current to less than what the circuit current limit is, the power consumption increases to 6mA + the current drawn by R5.

Can somebody speculate as to what is causing this?

Thanks

Oliver

 

(I have submitted this as a ticket and to asktexas over a week ago, with still no reply or help)

 

  • 0
    TI__Guru**** 150950 points

    Can you measure the voltage on both pin 15 and 16 for both cases?  Most likely, the IC is driving the FET harder (lower gate voltage) when the current limit is reduced.  Since the circuit does not reach the current limit, the IC continues reducing the gate voltage to try to increase the current.  That is the only way for it to increase the charge current.   So, the extra current is probably sunk by the gate drive circuitry.  This will enhance the FET slightly more but this will not cause the desired increase in current as the FET is already in the linear region, so the additional Vgs reduction does not affect the resistance significantly.