LMZM33606: Review request

Hi Preethi,

Looking at the schematic I'd suggest you change the output capacitance from 4 x 22uF to 4 x 47uF similar to the EVM. This way the minimum output capacitance of 150uF ceramic is met following Table 3 of the datasheet. Any electrolytic caps after the minimum ceramic capacitance is met will help with transient performance.

PCB Layout looks okay with one layout recommendation I have in the last bullet point:

• CIN and COUT caps placed close to respective VIN and VOUT pins to minimize lead inductance (√)
• AGND and PGND kept separate on PCB layout (√)
• Feedback node kept as small as possible (√)
• One thing I'd recommend is increasing the PGND copper plane on Layer 2 for better thermal relief. Right now it looks like only the blue copper plane in Layer 1 is the PGND. If this is a two layer board, then I would increase the PGND copper plane for added thermal design robustness. Note that the layout example in the datasheet uses a 4 layer board with multiple PGND copper planes for thermal relief. With 14W power consumption at 3.3V the expected power dissipation is a little under 2W based on Figure 7. You can use this power dissipation and your maximum ambient temperature to get an understanding of how much board area you would need for an adequate thermal design following equation 8 and Figure 52. 

Regards,

Jimmy