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TPS65218D0: Warm Reset

Will Jarrett
Expert 3395 points
Part Number: TPS65218D0
Other Parts Discussed in Thread: AM4378, TPS65218

I have a customer are using the TPS65218D0RSLT PMIC to support the AM4378BZDN80 Sitara.

They are seeing an issue we do not understand and are requesting your input and guidance per below description.

The PMIC receives a reset (pulled to ground by a switch…same as implemented in the AM437X GP EVM) through the WARMRST_N (called XRESET in our schematic below);

 

However, the PMIC DCDC outputs (other than DCDC5 and DCDC6) shut off and do not recover after the reset action until input power is cycled OFF/ON.

Do you have any thoughts/suggestions for us to continue our investigations?

  • 0
    TI__Genius 12735 points

    Hi Will,

    The expert for this device is currently out of office. I am reviewing the specifics of using this PMIC with that processor and will provide some feedback tomorrow.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    TI__Expert 3395 points

    We have also found that if the PMIC Strict mode is Disabled (bit set to 0), there is no issue with reset and recovery (PMIC rails power up normally).  We are thinking that this might point to an issue with OV during power up, but we do not see any issues when probing with a scope.  Thank you for your feedback and help with this.

  • 0 in reply to Will Jarrett
    TI__Genius 12735 points

    Hi Will,

    Just to confirm, is the customer using an AM335x processor or AM437x processor? According to the Powering the AM335x, AM437x, and AM438x with TPS65218D0 User's Guide, Warm Reset is only available when using the AM335x processor series. 

    If they are using the AM437x processors, do DCDC5 and DCDC6 ever shut off or do they stay high the whole time? It looks like the customer is triggering a power off sequence with the FSEAL (Freshness Seal) bit set, which keeps DCDC5 and DCDC6 from disabling.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    TI__Expert 3395 points

    Customer is indeed using AM437x.  Let me get some additional feedback for you.  Thank you.

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

    Thank you for the response.

    We are using the AM437.  During the reset (Warm Reset), DCDC5 and DCDC6 do not shut down...they stay high/ON (only DCDC1-4 shut down).  Regarding the FSEAL, once the Warm Reset is activitated, the PWR_EN also stays high.

    Upon reviewing the 437 TRM, it appears using Warm Reset is valid.

    FYI, we also have a PHY device (Microchip KSZ9131RNXI).  If we plug in the LAN cable to the RJ45, the same shut down issue occurs and does not re-start without a power cycle.

  • 0 in reply to Barry Carroll
    TI__Genius 12735 points

    Hi Barry,

    While the AM437x may be capable of using a Warm Reset feature, this PMIC is only able to support Warm Reset with the AM335x processor series. This is noted in both the TPS65218D0 datasheet in section 1.3 on page 2 and in the Powering the AM335x, AM437x, and AM438x with TPS65218D0 User's Guide in section 11. 

    In this case, I believe what is happening is that the PMIC is treating the warm reset request from the processor as a power off event and shutting down the device. I am not sure why this is happening, I am not extremely familiar with this PMIC and how it interacts with these different processors. Brian, the expert for this device, will be back in the office Monday and will be able to speak to why exactly this is happening. However, I can confidently say that this PMIC does not support the Warm Reset feature using GPIO3 unless using AM335x.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

    Attached is the AM4378 GP EVM we are using as guidance (uses the TPS65218 vs. the TPS65218D0 part we use) and WARM RESET function (Sheet 2...tied to the AM437 G22 port).AM437X_GP_EVM_3K0006_SCHEMATIC_REV1_5B.pdf

  • 0 in reply to Barry Carroll
    TI__Genius 12735 points

    Hi Barry,

    As seen in that schematic, GPIO3 is not used for the Warm Reset function. It appears to me that the nRESETIN_OUT of the processor is set to be an input and not an output and is connected to a switch/button that, when activated, causes the processor to trigger a warm reset cycle. This should involve pulling the PWR_EN pin low and then bring it back higher, based on my understand on this schematic. Is PWR_EN ever brought low when triggering the warm reset?

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

    We are not using the GPIO3 as the WARM RESET...it is tied to G22 (WARMRST_N).  The PWR_EN pin does not go low (it is also tied to RTC_PMIC_EN which is AD6).

    If possible, it may be most beneficial if we have a concall...is this an option?

  • 0 in reply to Barry Carroll
    TI__Genius 12735 points

    Hi Barry,

    We can set up time for a conference call, however I would recommend waiting for next week for the expert for this device to be back in office. He will likely be able to provide a solution without the need for a call and in the event of a call would be able to provide far more information and background on this PMIC/processor interaction than I can. 

    If PWR_EN does not ever go low then something else must be disabling the rails on TPS65218D0. Is there any communication through I2C happening when you activate the warm reset? Can you scope the I2C lines to confirm this? Is there anything else being done to the board other than activating the Warm Reset button when you see the rails being disabled?

    Best regards, 

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

    I understand...we will follow your recommendations for a concall.

    Regarding the I2C, these lines (SDA/SCL) stay high, but no I2C comms observed on a scope (we do not see this on the EVM either while on OR during the reset).

  • 0 in reply to Barry Carroll
    TI__Genius 12735 points

    Hi Barry,

    I am not sure how the device could possibly be going into a power off state without the PWR_EN pin going low or I2C disabling these rails. Can you scope the PB pin and see what is happening with that pin? That is the last thing I can think of is that pin is causing the device to shut off but this is unlikely. 

    If this does not provide a solution we will have to wait until the expert is back in the office to provide some suggestions on a solution.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

    The PB pin stays high (it is tied to the System Power Rail...5V). Note, PGOOD does go low once the reset occurs (which it should).  Only a power cycle returns the outputs.

  • 0 in reply to Barry Carroll
    TI__Genius 12735 points

    Hi Barry,

    The expert for this device is now back in the office. I have assigned this thread to him and he will provide an update by the end of the day tomorrow.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 90 points

    Hi Layne,

    Excellent, thank you!

  • 0 in reply to Barry Carroll
    TI__Mastermind 30280 points

    Barry & Will,

    Please confirm that the WRMRST_N (or XRESET) signal is connected to GPIO3 of the TPS65218D0 PMIC.

    It is not relevant how this signal is connected to AM437x processor if the PMIC is experiencing the issue.

    The WARM RESET feature of the PMIC is pretty straightforward: DCDC1 and DCDC2, which support DVS, are reset to the default value of 1.1V output voltage.

    The issue you are seeing is related to the narrow window of masking VOV and VPG faults during the DVS transition. See, the AM437x processor reduces its CPU load during the reset and the PMIC is likely trying to go from a higher voltage (1.35V, for example) to 1.1V with a large amount of output capacitance.

    Therefore, it is reasonable that changing the STRICT bit from 1b to 0b will resolve the issue because STRICT=0b disabled all the VOV (over-voltage) faults. Your problem can be fixed in one of 2 ways:

      1. Reduce the output capacitance on DCDC1/2 until the issue no longer occurs
      2. Permanently set STRICT=0b (either by adding it to the initialization routine of AM437x processor, or by re-programming the EEPROM memory of the PMIC)
      • Instructions for re-programming the EEPROM memory of the PMIC are provided in the TPS65218D0 datasheet
      • AM437x does not require STRICT=1b. This ultra-sensitive voltage monitoring is only required for AM438x (secure applications such as ePOS)

  • 0 in reply to Brian Berner
    Prodigy 90 points

    Hi Brian,

    Thank you for the response and inputs...excellent!

    We may continue with the STRICT=0b as this has resolved the issue (our only concern was OV protection of the AM437x).

  • 0 in reply to Barry Carroll
    Prodigy 90 points

    Brian,

    Quick question; on the TI EVM (schematic attached) the  WRMRST_N is not connected to the PMIC GPIO3.  Should this be used rather than the 437x RESETIN_OUTn (as the TI EVM)...or both?4024.AM437X_GP_EVM_3K0006_SCHEMATIC_REV1_5B.pdf

  • 0 in reply to Barry Carroll
    TI__Mastermind 30280 points

    Please refer to Figure 1 and Figure 7 in the Powering the AM335x, AM437x, and AM438x with TPS65218D0 User's Guide, which shows GPIO3 pin of the PMIC connected to a WARMRSTn pin of the processor.

    It is my understanding that this pin on the processor is the same as RESETIN_OUTn (pin G22) on the EVM schematic you shared, which should also be connected to the GPIO3 pin of the PMIC. The signal connects to every other IC on the schematic (Ethernet PHY, Touch-Screen Controller) that needs to be reset except the PMIC, but I cannot say why it was done this way.

  • 0 in reply to Brian Berner
    Prodigy 90 points

    Got it...thank you Brian!