The datasheet specify max IDSS and IGSS only at 25degC. I need to know the max value at 0 to 50 (or 40) degC.
And if you have tips about other tiny NMOS and PMOS with even lower leakage that would be welcome too.
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The datasheet specify max IDSS and IGSS only at 25degC. I need to know the max value at 0 to 50 (or 40) degC.
And if you have tips about other tiny NMOS and PMOS with even lower leakage that would be welcome too.
Hi David,
Thanks for your interest in TI FETs. You are correct that TI does not spec leakage over temperature. During product development a number of samples are tested to the datasheet over temperature. The attachment is a summary of the max IDSS and IGSS measured during this characterization. Please note, TI cannot guarantee this performance since it is not specified in the datasheet. We only guarantee IDSS<50nA and IGSS<25nA at 25degC as specified in the datasheet. The CSD13380F3 is probably the lowest leakge, small form factory N-channel FET that TI makes. In general, the FETs with single-ended gate ESD structure have very low leakage while those with back-to-back gate ESD structure are much higher leakage. I am including a link to a technical article on gate ESD structures for TI FETs as well.
Thanks. Do you have any arrays of MOSFETs with such low leakage? As far as I can see, the FemtoFET family does not exist as array, only single?
Hi David,
Thanks again for your interest in TI FETs but unfortunately, we do not make an FET arrays. The FemtoFETs are all single MOSFET devices. TI's FET product offering includes singles and a limited number of duals (independent, half-bridge, common source and common drain). The link below is a list of all the dual FETs.