• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 573 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5069: Supply into OUT pin and internal Zener diode stress

Walter Mueller74
Prodigy 40 points
Part Number: LM5069
Other Parts Discussed in Thread: TPS2663

Dear E2E support forum

I would like to use the LM5069-2 as rush current and power limiter, in a 24V supplied system. The system is equipped with large capacitive load, as energy storage, to bypass short interruptions of the 24V supply (up to 10ms).

(Side note about the design:
The LM5069-2 must limit the current/power at the connection to the 24V supply, but also after short interruptions or voltage dips. The reconnection of the system load back to the 24V supply is critical, because of the released load with its bias. It must supply constant power down to about 10V. The LM5069 keeps running because of the body diode in the FET.
I found all information for the design and I could check it on an evaluation board. It seems to work.)

In my design, I must recon with any low supply voltages, combined with large charged capacitors at the output. Under some conditions, the output capacitors could be also supplied from an alternate path up to the input voltage.
I see a critical condition, where the LM5069-2 is supplied with less than VPORit but with enough to enable the gate sink current. The diode between OUT and the GATE is then forward biased and discharges the capacitors at the output.

May it cause damage to the LM5069-2, if the OUT pin is supplied by a source, which keeps VIN by the body diode of the FET close but below VPORit (max. 8.0V).

Regards Walter

  • 0
    TI__Guru** 105361 points

    Hi Walter,

    Welcome to E2E!

    In such application, you would need back-to-back FET configuration like the one discussed in app note https://www.ti.com/lit/an/snva683/snva683.pdf

    What is the current level of your system and end equipment ? TPS2663 is the right fit to support voltage interruptions. Please refer datasheet and Figure 45 in the datasheet and let me know if it suits or any further questions.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    Prodigy 40 points

    Hi Rakesh

    Thanks for the hint.
    Instead of a design with the LM5069-2, with a lot of additional circuits, the TPS2663x seems to be the better choice. I will check it out and supposably change the design.

    The needed solution is close to the "TPS2663x datasheet figure 43".
    (By the way: check figure 43 and figure 45 in the datasheet.)
    Cout 2.2mF, Pout max 30W.

    Just to know:
    The design with the LM5069, without a back-to-back FET, would be critical?
    (OUT pin supplied by a source, with VIN close below VPORit.)

    And, by the way:
    Please check also the datasheet of the LM5069 on page 20.
       9.2.1.2.3 Select Power Limit
       To avoid …
       To avoid …     <- missing the right text, seem to be a copy/past mistake

    Thanks, and best regards,
    Walter

  • 0 in reply to Walter Mueller74
    TI__Guru** 105361 points

    Hi Walter,

    You would need reverse current blocking feature to avoid discharging the Cout during power fail event. so, back-to-back FET configuration is needed with LM5069.

    Thanks for pointing the text correction. We will update in the next datasheet revision.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    Prodigy 40 points

    Hi Rakesh

    Thanks for the feedback.

    It is not a clear answer to my question, but the need of the back-to-back FET implies, that it would/could be a problem (OUT pin supplied by a source, with VIN close below VPORit).
    I miss in the datasheet a specification of the OUT pin or the maximal allowed capacity on the output.

    Thanks, and best regards,
    Walter

  • 0 in reply to Walter Mueller74
    TI__Guru** 105361 points

    Hi Walter,

    In back-to-back FET configuration as shared in app note, https://www.ti.com/lit/an/snva683/snva683.pdf The OUT pin does not get power when the both the FETs are turned-OFF so diode between OUT and the GATE does not get discharge path for the output capacitors.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    Prodigy 40 points

    Hi Rakesh

    The solution/design with the back-to-back FET is anyway clear to me.
    I know, that I must use it, if I would make my design with the LM5069.

    See it just as a note, that I do not find the information in the datasheet, that guides me to that needed solution.

    Thanks for your patience, and best regards,
    Walter