TPS3831: Question on Figure 13, "TPS3839 Transient Rejection" in data sheet.

Hi Peter,

The drop in % is relative to the VDD in its valid condition, so the start value for glitch immunity.

I think you're confused about the intended language here. The correct way to look at it is: if Vdd dropped by 5%, the device would reset if that dip lasted longer than approx. 12 us. If it lasted shorter it would not reset. Similarly, if Vdd dropped by 20%, the device would reset if the dip lasted approx longer than 32us, and would not under that value.

Does that help the understanding? Let me know if you have questions.

Thanks,
Abhinav.

Hi Abhinav,

Thanks for the reply. When you say "Vdd dropped by 5%", do you mean 5% below VIT-, regardless from what level the drop started from? Assume VDD=4V, VIT-=3.08V, 5% below that would be 2.926V. So if something creates a dip from 4V down to 2.926V (5% below VIT-, or 26.9% below the starting 4V), then a pulse longer than ~12us creates a reset, but not a shorter one. Is that correctly understood?

Seems a bit odd that a large dip of say 30% (interpreted as 30% below VIT- in this case), would only cause a reset for a ~47us pulse. So a short shallow pulse creates a reset (say 5% dip, 15us pulse), while a long deep pulse does not (say 30% dip, 45us pulse). It seems I am missing out something here...

Regards,
Peter

The drop is below the level of VDD, not VIT-. The value would be 4V that you're looking at. Your understanding for why it is odd is inverse. I think this is because you are viewing this as a function of VIT- and not VDD.

Thanks,

Abhinav.

So if I am running on Vdd=4V, assuming VIT-=3.08V and I get a dip down to 2.93V, What pulse length can I cope with? Do I use 27% (total dip from 4V) resulting in a minimum pulse length of 43us creating a reset, or 5% (the amount it goes below VIT-) resulting in a minimum pulse length of 12us creating a reset? 

Or explain using some other example.

Regards,

Peter

Peter,

You would use 27%, thus using 43us as the spec.

Thanks,
Abhinav.

Hi again,

I don't see why the starting level of the pulse matters. If I in one case have Vdd=4V, get a dip down to say 2.9V (below the VIT-=3.08V) I have 27.5% dip resulting in 43us minimum pulse length for reset. So any pulse shorter than that would be ok.

On the other hand if I have Vdd=3.3V and get a dip down to 2.9V (below VIT- by the same amount as above) I have ~12% dip resulting in 20us minimum pulse length for reset.

Both cases are below VIT- by the same amount, but gives different pulse length. Shouldn't the reset times be equal?

/Peter

Peter,

You're right, I see the confusion here, and I think I misspoke on my part. The spec we should actually be looking at is drop below VIT, and the confusion lies in the language on the graph where we say drop of VDD below VIT. In the case described above, the times should be the same.

Thanks,
Abhinav.

Hi again,

But then we are back at the starting point where a larger percentage value relates to a longer pulse needed for reset. A 5% dip (i.e. a dip that reaches 5% below VIT- level) implies that pulse lengths longer than 12us results in a reset, while a 20% dip (20% below VIT-) requires the pulse to be longer than 32us to result in a reset. That may be correct, I don't know. But to me it seems a bit counter-intuitive that a larger dip would result in a longer pulse being tolerated. I would expect it to relate more like shallow dip (less %) -> longer pulse tolerated, deep dip (higher %) -> shorter pulse. But that is not what the figure says, at least not the way I interpret it. 

/Peter

Hi Peter,

The way it is designed, it implies that a larger dip would need a little bit longer than a shorter dip to recover and not be considered a glitch. If a shallow glitch occurs, it is expected that it would return to the voltage level relatively quickly, whereas a deeper glitch would take more time to deramp and ramp back up. The figure is correct. Does that make sense?

Thanks,
Abhinav.

Hi Abhinav,

So the IC tolerates a deeper dip that last longer but could reset a more shallow dip that last a shorter time? Sounds a bit odd to me. The whole purpose of a reset circuit is to protect against dips that are deep and long such that the voltage would fall too much and potentially harm circuits with a min voltage limit. If it is as you say, this circuit doesn't provide any such protection. I would have expected a more "area under the graph" approach where a deep dip requires a shorter time to recover before reset, while a shallow dip can be allowed for a longer time before resulting in a reset.

/Peter 

Peter,

Looking at your comment, the logic makes sense and is leading me to believe we have either an error in our datasheet or the explanation is unclear to me as well. I will consult with our systems engineer on this topic and reply back to you when I get more clarity. In theory, the supervisor should work as you describe, and eliminate short glitches.

Thanks,

Abhinav.

Hi Abhinav,

Did you get any answers from the systems engineer?

Regards,

Peter

Hi Peter,

Still working on closing this topic with the engineer. I will push for an answer urgently.

Thanks,
Abhinav.