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UCC24636: RVPC,RVSC

kura
Genius 4790 points
Part Number: UCC24636

Our customer consider to use UCC24636 with High-side SR configuration with Bias winding.

Please check attached fole and advise about RVPC,RVSC.

UCC24636.xlsx

  • 0
    TI__Mastermind 33810 points

    Hello Kura-san,

    Thank you for your interest in the UCC24636 SR controller.

    The original values of the resistance calculations in the attached file appear to be correct, based on the high-side SR configuration equations.
    I cannot determine why the device is behaving incorrectly with the information provided.

    For the Io = 0A case, the device is operating normally.  It has gone into stand-by mode because the switching frequency is < 5kHz (< 64 pulses within 12.8ms).
    For the Io = 1.2A and 3A cases, the device is not operating as expected.

    I wonder if the actual customer circuit has the VPC and VSC pin connections mixed up.
    Can you please provide the customer schematic diagram of the SR circuit, along with the values for Rb, Cvdd, and Cvsc (as indicated in Figure 2 in the .xlsx file).

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Genius 4790 points

    Ulrich-san

    Thank you for your support.

    We got  customer circuit information.,We would liike to send this to you .

    Please  let us know your adrress.

    Regards,

  • 0 in reply to kura
    TI__Mastermind 33810 points

    Hello Kura-san,

    From the files sent I see that the VSC and VPC connections are correct.  I also see that the VSC capacitor position is left open (value = 0), although it is shown on the schematic diagram.  I think it may be possible that switching noise may couple to the VSC input and speed up the internal ramp which can result in short gate-drive pulses. 

    I recommend that you add a 1000pF cap from VSC to the device GND (Cvsc = C57). 

    I also see that C58 is a 1000-pF capacitive load on the gate-drive output in addition to the actual MOSFET gate.  I don't know why that was added, but I suggest to remove it or reduce it to 100pF, at least for test purposes.

    One other suggestion is to add a 22pF cap across R61 (VPC to device GND) in case noise may be affecting VPC.  Too much capacitance will delay turn-on of the SR, but that is not a concern right now. It can be reduced later. 

    The main objective is to get reasonably wide and consistent gate-drive pulses first, then tune the timings later for optimal performance.

    Finally, make sure that the VDD cap C56 does not have significant value reduction from the DC-bias effect.  It should be X7R, 50-V rating, in 1206 case size (3216 metric).  Smaller cases and lower voltages can lose a lot of capacitance even at only ~15V.  Diode D51 should have ultrafast reverse recovery.

    Regards,

    Ulrich

  • 0 in reply to Ulrich Goerke
    Genius 4790 points

    Ulrich-san

    Thank you for your advise.

    They could find that ON time become long when they add 5pF(VPC to device GND).

    They continue to modify their circuit according to your advice.

    When we get additional result from them we report to you.

    Regards,

  • 0 in reply to kura
    Genius 4790 points

    Ulrich-san

    Thank you for your support.

    We got result of their modified circuit.

    >add a 1000pF cap from VSC to the device GND (Cvsc = C57). 

    ---> Q  broke immediately

    > remove it or reduce it to 100pF, at least for test purposes.

    --->They couldn't find any changing.

    > add a 22pF cap across R61 (VPC to device GND) in case noise may be affecting VPC. 
    --->They could find that ON time become long when they add 5pF(VPC to device GND).
          But when add over 5pF,they found FET didn't ON. 

    > should be X7R, 50-V rating, in 1206 case size (3216 metric).  
    --->They are using X7R 50V 1uF.

    >Diode D51 should have ultrafast reverse recovery

    ⇒They are using FRD.

    They continue to evaluate this at high voltage.

    We will send result to you thru another mail.

    Regards,

  • 0 in reply to Ulrich Goerke
    Genius 4790 points

    Ulrich-san

    Thank you for your support.

    We got result of their modified circuit.

    >add a 1000pF cap from VSC to the device GND (Cvsc = C57). 

    ---> Q  broke immediately

    > remove it or reduce it to 100pF, at least for test purposes.

    --->They couldn't find any changing.

    > add a 22pF cap across R61 (VPC to device GND) in case noise may be affecting VPC. 
    --->They could find that ON time become long when they add 5pF(VPC to device GND).
          But when add over 5pF,they found FET didn't ON. 

    > should be X7R, 50-V rating, in 1206 case size (3216 metric).  
    --->They are using X7R 50V 1uF.

    >Diode D51 should have ultrafast reverse recovery

    ⇒They are using FRD.

    They continue to evaluate this at high voltage.

    We will send result to you thru another mail.

    Regards,

  • 0 in reply to kura
    TI__Mastermind 33810 points

    Hello Kura-san,

    I have received the file in the other mail and the waveforms there helped me think of some possibility for the missing DRV pulses.

    The symptoms of partial DRV outputs at 300V input, varying a little with load, and no DRV at 400V made me think of some kind of protection response.

     

    I found in the datasheet, Section 8.3.4.1 and Section 8.4.4 both indicate that an over-voltage condition on the VPC input for > 500ns will prevent the DRV output for that switching cycle. OV on VPC can occur if Vvpc > 2.6V.

    I wonder if the problem may be an over-voltage at the VPC input. It could be a marginal condition at 300V, but always present at 400V input.

    Please ask your customer to investigate the possibility of excess voltage at VPC.

     

    Regards,

    Ulrich

  • 0 in reply to Ulrich Goerke
    Genius 4790 points

    Ulrich-san

    Thank you for your support.

    We got some waveforms from customer.

    Please check Private Message.

    Regards,

    Kura

  • 0 in reply to kura
    TI__Mastermind 33810 points

    Hello Kura-san,

    I have sent a reply with comments on the waveforms, also by Private Message.

    In summary, based on the waveforms shown in the file, I suspect that the pcb connections do not follow the schematic diagram.
    The schematic diagram shown in the file is correct.
    I recommend to compare the pcb connections to that of the schematic, and correct any discrepancies that are found.

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Genius 4790 points

    Ulrich-san

    Thank you for your support.We got additinal information from customer.

    Customer checked pcb connections is true.

    And capacitor  value between VPC to device GND in all sheet are correct

    About turns ratio of the windings:

    Np:17

    Ns:5

    Nb:2

    Regards,

    Kura