TPS3840: Reset output by MR is not working properly.

Hi Kevin,

Looking at the "Signal capture #2 (Reset output and MR* input)" waveform, the /MR voltage waveform is between 750mV to 1V.  The /MR logic low input spec is 600mV or lower.  Have the customer remove C76 and repeat the test.  Please let me know if there are any other questions.

Thanks,

Ben  

Hi,

I have attached another signal capture.

It was MR* input and RESER output signal capture after removing two parallel capacitors (C76, C77) on MR* input line.

As you can see, there seems to be no problem with MR* input signal.

However, RESET output signal behavior is very strange.

Please give your advice why RESET output is not working properly.

Regards,

Kevin.

Hi Kevin,

The photo below shows the /RESET signal working correctly.  When /MR is asserted, /RESET is asserted after ~450nS.  Base on the /RESET waveforms, it appears that CT is floating.  The time (tMR_tD) is around 50uS.  Can you verify if there is a 220nF capacitor connected to the CT pin to GND?

Thanks,

Ben

Hi Kevin,

Can you include the CT waveform with /MR and /RESET?  I suspect the voltage on the CT pin does not have enough time to discharge with a short assert /MR duration.

Ben  

Hi Ben,

Thanks for your feedback.

But I'm confused. If 220nF capacitor is not connected to GND, then it means that CT is floating.

If so, the reset time delay is around 50us and this is minimum value.

If 220nF capacitor is connected between CT pin and GND correctly, the reset time delay is increased than 50us.

In any case, the reset time delay should be longer than 50us.

Please correct me if there is something wrong in my understanding.

Regards,

Kevin.

Hi Ben,

Can you include the CT waveform with /MR and /RESET?  I suspect the voltage on the CT pin does not have enough time to discharge with a short assert /MR duration.

>> I will attach it as soon as possible.

Regards,

Kevin.

Hi Kevin,

You are correct that the reset time delay should be longer than 50uS when using a 220nF capacitor on the CT pin to GND.  Getting the CT voltage waveform will help us understand the issue and hopefully help resolve the problem.

Thanks,

Ben 

Hi Ben,

I have attached /MR, /RESET and CT signal capture.

Please check it and give your advice.

As you can see at left side, if /MR falls to low for a very short time like glitch, /RESET is asserted although it is also very short time.

My understanding is correct, /RESET should not fall to low in this case.

Can you please let me know why /RESET output is asserted by very short-term /MR input?

And the customer checked /RESET output after removing CT capacitor, i.e. 220nF.

In this case, /RESET should remain low level for about 50us. Right?

However, the result was the same as the capture on the right.

Regards,

Kevin.

One more question.

The customer is using TPS3840PL26DBVR.

It is a Push-Pull variant and the datasheet describes that it does not require a pull-up resistor.

But the customer applied a pull-up resister on /RESET output.

Can this pull-up resister cause a problem?

Regards,

Kevin.

Hi Kevin,

I think I see the problem.  The /MR pulse is so short that the voltage on the CT pin does not react at all.  Can you remove the CT capacitor and repeat the test?  The voltage on the CT pin should go down without the capacitor.  

Adding a pull-up resistor on the /RESET pin should not cause this issue but just for experiment, can you also remove the pull-up resistor?

Thanks,

Ben

Hi Ben,

Can you remove the CT capacitor and repeat the test?  The voltage on the CT pin should go down without the capacitor.  

>> I have heard that the customer already repeated this test after remove CT capacitor.

But the test result was the same. /RESET is asserted very shorter than expected.

I will check it again anyhow.

Adding a pull-up resistor on the /RESET pin should not cause this issue but just for experiment, can you also remove the pull-up resistor?

>> Okay. I will check it and let you know the result.

Regards,

Kevin.

Regards,

Kevin.

Hi Ben,

Please refer to the below picture.

It was signal captures after removing the capacitor connected to CT pin. (CT pin was floating)

As you can see, the voltage of CT pin goes down and then slowly returns to high level.

And /RESET delay time increases a lot compared to before but it is still shorter than 50us.

Can you please check the signal captures and give advice?

FYI, removing the pull-up resistor connected to /RESET output pin does not affect the result. 

Regards,

Kevin.

Hi Kevin,

Thank you very much for the scope capture.  This explains a lot what is going on.  The /RESET delay, on the scope capture, is shorter than 50uS, which meets the datasheet spec.  Basically, the reset time delay should not be more than 50uS when the CT pin is left open.  Therefore, the part is functioning correctly when CT pin is open.

Having a 220nF capacitor on the CT pin and the scope capture showing (see below) the voltage on the CT pin not discharging to GND means the assert time of /MR is not long enough.  From the scope capture, the assert time of /MR is too short resulting in the voltage on CT to stay at its original value.  Therefore, the assert time on /MR needs to be longer to have the CT pin voltage discharge to GND.  

Just for your reference, the paragraph on top of page 18 explains the situation you are experiencing with your circuit.

Please let me know if you have questions. 

Thanks,

Ben 

Hi Kevin,

If I have answered your questions to your satisfaction, please click on "resolved" to close the thread.  Thank you and have a nice day!

Ben

Hi Ben,

Thanks for your update.

I will check if the longer /MR assert time solves the problem and let you know the result.

By the way, I have more questions.

1. Is there any reference table for /MR assert time depending on the capacitor value connected to CT pin?

For example, if 100nF then /MR assert time have to longer than 400ns so that CT pin voltage discharge to GND and if 200nF then /MR assert time have to longer than 500ns, etc.

2. The datasheet describes that /RESET is not asserted if /MR assert time is less than tMR_PW(/MR pin pulse duration to initiate reset, typical 300ns)

The customer would like to know why /RESET is asserted although /MR assert time was very shorter than tMR_PW,.

Can you please explain this?

Regards,

Kevin.

Hi Kevin,

There is no table referencing the /MR assert time to the capacitor value connected to the CT pin. 

From the schematic, it is showing that a 220nF capacitor is connected from the CT pin to GND.  Base on equation 4 from pg 17 in the datasheet, the delay time is calculated to be around 136.22ms.  Try a /MR assert time of greater or equal to 1% of the delay time (1.36ms or longer).

To your second question, the scope photos that you have provided shows a /MR reset time of greater than 300nS.  

Thanks,

Ben

Hi Ben,

Got it.

Thanks for your update.

I will update the result as soon as I get it from the customer.

Regards,

Kevin.

Hi Ben,

The customer have confirmed that /RESET is working properly if they assert /MR more than 1ms.

By the way there seems to be some confusion in the datasheet description for /RESET output by /MR input.

The following is a description of /MR input in the datasheet.

There are two descriptions for /RESET output by /MR input.

1. A logic low on /MR with pulse duration longer than tMR_RES (typical 700ns) will causes reset output to assert

2. Reset not asserted Pulse width less than tMR_PW (typical 300ns)

The latter tell me that /RESET will be asserted if /MR is asserted more than 300ns. 

You also confirmed this.

But the former tell me that /RESET should not be asserted if /MR is low less than 700ns.

I'm confused.

Can you please explain the exact behavior of /RESET output depending on /MR input?

FYI the customer has been using a RESET IC in many products and also has a plan to replace the existing RESET IC by TPS3840.

So please help me to give exact information.

Regards,

Kevin.

Hi Kevin,

The statement:

"1. A logic low on /MR with pulse duration longer than tMR_RES (typical 700ns) will causes reset output to assert"

is not correct.  Thank you for pointing that out to me.  Everything else that we have discussed is correct.

The timing diagram is correct as well.  Please disregard the statement.

Thanks,

Ben

Hi Ben,

Understood.

I will resolve this ticket if there is no additional question from the customer.

Thanks for your supports.

Regards,

Kevin.

Hi Kevin,

Glad to be of help!  Just let me know if you have any more questions.  Thanks!

Ben

Hi Ben,

From the discussion with the customer, TPS3840 /RESET output behavior seems to be different from what they want.

So the customer want to get your confirmation again on /RESET output timing characteristics by /MR input before making a decision.

Please review the following and confirm if /RESET output works like that.

Let's assume the minimum /MR pulse duration to initiate /RESET output is 300ns, i.e. tMR_PW.

And also assume the minimum /MR pulse duration for CT pin to discharge is 1ms.

- Case #1. /MR is asserted shorter than 300nsec.

  >> In this case, /RESET output is not asserted, i.e. /RESET output continues to keep high level.

- Case #2. /MR is asserted longer than 300nsec but shorter than 1msec.

  >> In this case, /RESET output is asserted at 400ns. (I assume 100ns delay between /MR and /RESET)

       However /RESET output goes back to high level when /MR goes back to high level because CT pin is not discharged to GND.

- Case #3. /MR is asserted longer than 1msec, for example, 1.1msec.

  >> In this case, /RESET output is asserted at 400ns and deasserted after when the programmed reset time delay expires.

Please correct me if there is something wrong in my understanding.

Additional questions.

- In case #2, what is /RESET output pulse duration? I'm not sure but I think it is (/MR input pulse duration - 300ns).

- Do all TI RESET ICs, which can program  the reset time delay using CT cap like 3840, operate like case #1 ~ #3?

Regards,

Kevin.

HI Kevin,  

See my response below in green:

- Case #1. /MR is asserted shorter than 300nsec.

  >> In this case, /RESET output is not asserted, i.e. /RESET output continues to keep high level.

Correct

- Case #2. /MR is asserted longer than 300nsec but shorter than 1msec.

  >> In this case, /RESET output is asserted at 400ns. (I assume 100ns delay between /MR and /RESET)

       However /RESET output goes back to high level when /MR goes back to high level because CT pin is not discharged to GND.

Depending on the capacitance on the CT pin, the CT pin may not have enough time to discharge resulting in /RESET being de-asserted sooner than the programmed delay.

- Case #3. /MR is asserted longer than 1msec, for example, 1.1msec.

  >> In this case, /RESET output is asserted at 400ns and deasserted after when the programmed reset time delay expires.

Please correct me if there is something wrong in my understanding.

Not correct.  Depending on the capacitor value on the CT pin, if the /MR is asserted for 1msec and the CT pin is open (no cap on CT pin), the /RESET output will de-assert in less than 50uS.  See waveform below:

- In case #2, what is /RESET output pulse duration? I'm not sure but I think it is (/MR input pulse duration - 300ns).

Depending on the capacitor value that is placed on the CT pin.  The rule of thumb is /MR assert time needs to be 1% of the /RESET time delay.  For example, if you use a 10nF capacitor on the CT pin, you will get a typical /RESET time delay of 6.2mS.  Therefore, the /MR assert time should be 1% of 6.2ms or 62us.

- Do all TI RESET ICs, which can program  the reset time delay using CT cap like 3840, operate like case #1 ~ #3?

The key is the timing diagram shown above (case #3)

Please let me know if you any other questions.  

Ben

Hi Kevin,

It appears that the timing diagram did not appear in the my reply.  You can find the diagram in the TPS3840 datasheet on page 18 figure 47.

Ben