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LMR33630: "optimal" current operating range for the IC?

Jim Smith1
Prodigy 160 points
Part Number: LMR33630

Hello,

Second forum post / question from me here, separate from the other...

I have used the WEBENCH tool to design three different DC/DC power rails, from an external DC supply. The power rails are put on a small pcb meant for a modular world of end products, meaning that various instrument modules will be hooked up to the rails by the end user, and the end user understands the current limits for each rail and buys a power pcb that matches their need. I will offer this one power pcb as a product. It offers +12V , -12V, and +5V.  

My question is... If for any given rail I use the maximum LMR33630 current, which is 3A, but the end user only ever taps a smaller portion of that rail, will the LMR33630 suffer from unnecessarily poorer performance?

In other words, if i suspect that a rail that I have designed at 3A will only ever be tapped for around 1A, would it be wise to downgrade the rail circuit to only offer perhaps 1.5A?

This was a suggestion from one of my PCB designers, at least that i should look into the LMR33630 a bit more to decide if i should downgrade some rails. "Optimal performance range" for the IC being the concern.

Is there significant performance benefit from downgrading the current designed? Perhaps is it just thermal/wasted energy? 

Is this really only a concern if the power is all coming from a battery, and thus the wasted energy is discharging the battery faster than it needs to? I suspect that is the case, but wanted to check to see if there is other performance benefit from downgrading the current for each rail closer to what will be used. 

The benefit of keeping the rails set for higher current is that it can of course work for some users who do require it. 

Thanks!

  • 0
    TI__Mastermind 35210 points

    Hello Jim,

    If operating at continuous frequency, which for 1.5A load it most certainitly will, going between 1.5A, 2A, or 3A device of the same family will cause no change in eff fig as the losses remain the same (power stage is equal).

    Often for higher power device, say >4A, RDS of the FETs will be lower for a converter to accommodate the higher power capability, by reducing loss within the IC. Same thinking remains for higher power device family. At say 3A load current, all 4A, 6A, and 8A trims losses will remain the same.