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TPS73510 stability and noise

Daniele Donadoni96
Prodigy 90 points
Other Parts Discussed in Thread: TPS795

I need a very low noise LDO to generate a +3.3V analogue voltage form +5V supply. On the same board a need +3.3V and +1.2 V for FPGA. For cost reason I would use only one LDO part number and I’m oriented on TPS73501. I have the following question:

1) Output capacitor requirements.

Data sheet and EVM require for stability a standard ceramic X5R/X7R capacitor higher than 2.2 uF with ESR lower than 1 Ohm. ESR = DF*Xc=DF/2ΠfC (f= 1KHz for C<10uF). Standard 10 V, 2.2 uF capacitor from Kemet, AVX or other has ESR higher than 1 Ohm (DF% around 5%). Where is the mistake ?

2) Output capacitor requirements.

I would use a 10 uF capacitor.

Is there a maximum limit of output capacitance (minimum limit on ESR) for stability ?

3) Output noise

Total noise characteristics are specified only at 1 mA and for TPS73525.

Is it possible to have information about TPS73501 noise especially when use in 3.3V output configuration ?

4) Unitary-gain configuration

To generate a 1.208V it’s possible to tie OUT to FB pin without Cfb. To improve noise and preserve stability is it possible to use a Cfb capacitor ?

  • 0
    TI__Expert 8890 points

    Hi Daniele,

    What is your output current for each output. 

    1) &  2)   I would look at the standard "ceramic" capacitors.  Yes, it can be difficult to find inexpensive electrolytic capacitors with the correct dissipation factor/esr combinations.  But the good news is that the 10uF ceramic capacitor is typically the least expensive capacitor per ufarad on the market.  I have found that the performance is very good using the 10uF cap as you suggest.  Please note that the "maximum esr" (1ohm) is the max esr to maintain stability - and so you really don't want to have that much esr.

    3) At this point, I have not found the old data for noise at other loads than 1mA.  But I am still looking.

    4) This part does not suffer so much from instability but rather it has lower phase margin at higher Vout.  For your case, where Vout = 1.2V, there will be no stability or phase margin issues.  Yes, just tie the OUT to FB - and this will work fine.  Connecting the OUT to FB is electrically better than using the Cfb to reduce noise because this the "tightest" way to couple, or feedback noise, to the reference.

    Have you looked at the TPS795?

    Bill

  • 0 in reply to Bill Stokes
    Prodigy 90 points

    Hi Bill,

    board supply is +5V to +6V from a DC/DC converter. To reduce supply noise I’m going to use a first LDO to create a voltage around +4.3 V, then two LDO to create +3.3V analogue (Iout 200 mA low noise required) and +3.3V digital (Iout 50 mA). From +3.3V digital I derives +1.2V digital (Iout 50 mA).

    I can’t use TPS795 because Vin max is +5.5 V.

    I don’t understand is there a minimum output capacitor ESR value to guarantee stability.

     

    Thank you in advance.

     

    Daniele.