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UCC28780: ucc28780- AGAIN SWS STUCK AT 2V

Part Number: UCC28780

Ulrich:
3rd proto got stuck with SWS pin at 2V. 121 Ohms ( R22 in Eval kit)  shows 12.5 mA current. HVG stuck at like .4V.

We have tried reflow of new controllers suspecting pad cold solder. Did nothing.

We spent a day dead bug fashion hookup of the controller to make sure all pins get connected.

Exact the same observation.

Do these results tell us anything about the underlying issue?

i.e

- Depletion source is stuck at 2v

- HVG at .4 v

- R22  carries 12.5 mA

We have found no errors in the 3rd proto. Yet, on first power-up, it worked exactly as expected. We then hooked up the xmfr. & so far, never got it back to work.

Yet we are trying to follow the Debugging Startup failures Document as well as we can.

Other two protos we had to abandon due to some damage from repeated rework. But as you recall, we had the start-up working. There was  no PWML so our idea was to go to 3rd proto in order to eliminate chances of open circuits .

Any insight will be immensely helpful as we are dead against a serious situation. 

robin

  • Hello Robin,

    There is something systematic going on, given that first power up does allow SWS and VDD to rise to 17.5V, the cycle between that and 10V.
    (The no-PWML is a different issue.)  Then subsequent power ups result in stuck-at 2V and HVG stuck-at 0.4V.

    I am a little confused about the 12.5mA current in "R22" equivalent part on your board which is R24. 
    a) let's stick with reference designators on your board.
    b) let's make sure the numbers make sense.
    12.5mA through 121R means ~1.5V across it.  This means if the Fet source = 2V, then SWS = 0.5V, OR, if SWS = 2V, then FET source = 3.5V. 
    There are 2 conflicting statements in your post, above.

    Also, if there is 12.5mA flowing through your R24 (121R) it has to be going somewhere. The IC itself draws only 70uA before it starts up.   
    Assuming the IC is not blown, let's
    c) verify that there is a constant 1.5V across only R24 (121R x 0.0125A), not to GND or other points.
    d) if true, find out what is loading VDD.  What goes in SWS must come out VDD to charge Cvdd and anything else hanging on the 12VGRF rail.
    e) verify that Vvdd is < Vsws; if Vvdd = Vsws, then little to no current is flowing to VDD (especially since internal resistance is at least 1K and may be up to 12k) so 12mA can't flow through this path without substantial voltage difference).  Remove D5, the 22V Zener on SWS, to eliminate that path.
    f) Being a depletion Fet, if the source gets higher than the gate by a few volts it will pinch itself off.  But HVG is tied to SWS internally (see Fig 29 of DS) so HVG should be approx. = to Vsws if Vsws was stuck.  On the other hand, if HVG is stuck at 0.4V, it will automatically stick SWS to a few V above HVG.
    Check D4, the 22V Zener on HVG, and remove it to see if it is somehow holding HVG down. Also check that C22 (2200pF cap on HVG) is not shorted/damaged from a stress crack due to board flexing or excess heat from soldering (just trying to cover all the bases). 

    All of the above should apply whether you are using the CPC3909 or have changed to BSS126. 

    Finally, since each board did get VDD to 17.5V at least once (if I understand it correctly), but not on subsequent power-up attempts, it seems evident that something is getting damaged after the first power up, possibly during the power down. Maybe there is an overstress such as a voltage spike if the input power is applied with a toggle switch over long lead wires, for example, which could lead to an inductive kick when abruptly toggled off.  Maybe you don't do this, but again, I'm just trying to cover all bases (at least those that I can think of).

    Hopefully the IC itself is not getting damaged, but if it is not any of the external parts, check the resistance of HVG to GND with the board unpowered. Compare to a good unit.  It should be several hundred K.  HVG has a maximum voltage rating of 25V.  If it is measuring low ohms to GND (without any other parts attached), then you'll have to monitor and find out how HVG can come to be overstressed after the first power up.

    Regards,
    Ulrich

     

  • Ulrich:
    Very kind of you to give a detailed analysis of the situation.

    Apologize for not reading my txt more stringently to make sure the meaning was clear.

    Agreed, let us stick to our sch ref desigs.

    Here are few clarifications:

    - True: all these we are seeing at very low VBULK values do not depend upon the depletion type FET  being used.

    Yet,  note that in Proto 2 , we had reproduced the exact same results as the Eval kit at SWS & HVG nodes. Exact signature voltages. 

    And we knew exact reasons for getting these results. 

    But there was no PWML. All the way up to 100V if not higher.

    But for some reason, REF  level was low or something like that, I do not have records of why we removed the controller but could no longer install it back manually.

    That led to Proto 3 assy. Which worked right the first application of VBULK- only ramp up & low voltage levels. No more than 10V or so.

    Excited, We decided to complete the xmfr installation with AUX & Secondary etc...& Upon doing so, we could not get the startup signature voltages at SWS & HVG. They got stuck at the values mentioned above.

    We tried 2 controller  installs, same results- stuck at low voltages.

    1- 12.5 mA . It was calculated from the voltage across R24. So the drop was approx 1.5v

    SWS was at .2 or something. Source of Q5 at 1.7V at VBULK 6V  , HVG at I think .2V

    iSSUE WAS THAT THE sws & hvg NODES were stuck at these values no matter VBULK.

    We did not go any higher than this VBULK because you do not want R24 or Q5 burn up.

    --->>> did not determine the path of 12.5 mA. Cannot be in the startup loop. All values are high KOhm & none was shorted.

    We have checked zeners & they appear to be ok..but not removed. WILL DO SO TODAY IF THIS COMES TO PASS AGAIN.

    If it is anything, I suspect floating exposed pad somehow causes it to draw this current & returns through GND pin. To measure GND current would require destructive means to add current measuring loop...

    So our focus went to correct guaranteed soldering of the exposed pad in all new installations.

    And this is what we are doing now.

    2- we measured with Fluke multimeter all DCR values around the Eval kit. Did so on Proto3 ( & also on proto2 & proto1). Without controller & with.

    3- I applied 5V on all meaningful nodes & measured dc bias values- all appeared consistent. Without controller in assy.

    Apart from differences due to different inputs, these values correspond pretty well.

    4- In order to explore cold solders, I could think of applying 400 kHZ 5V pulses at all meaningful nodes( no controller in assy) on the hypothesis that cold solder "impedance" behavior is detectable as contrasted to "good" solder joints at such frequencies.

    Give no gotcha was found, I was left with another likely candidate: solder p[aste particles splattered under the controller because we are putting paste manually through the stencil.

    So we devised an installation procedure to prevent that from happening. Got ultra-sound cleaner, solder masking liquid.

    We applied it very successfully albeit it took  a day to get it right. Cleaned in ultrasonics.

    Unfortunately, we got stuck with pin 14 shorted internally to GND at 5.4 Ohms. We had one before on pin 9 about 10 days ago.

    Had to remove the chip : and found the exposed pad area quite shapely & clean.

    We suspected ESD from hot air in the last short case. 

    So today we got a humidifier running. 

    I get all of your points. So let us keep hammering at the issues until we get it  through 3 PWMLs

    In order to explore the rest of the chain is right, we are forking out or efforts.

    -1 Re-Assy of proto1 & proto2  without controller as if "open loop"- and apply external 5V at REF, external Pulse as PWML and test all nodes & waveforms again . Upper GaN check is a bit complicated. but I think PWML doing a flyback at reasonable VBULK & power will give us CS, Output waveforms due to UXCC24612, diode emulation of EPC2034,  RESULTS OF 5V at VREF will give us some DC info as well.

    -2 Assemble again with more care Proto3 using new controller.  Test that only for startup & 3 PWML study.

    I will share asap results we have.

    Thanking you again for your continued help. We got to get this product out asap!

    robin

  • Hi Robin,

    Good luck with further debug and power-up.

    Assuming you are successful to get VDD up to 17.5V to begin the start-up sequence of Figure 30 (page 28 of datasheet), please keep in mind that to get any PWML, RUN has to go high first, but to get RUN, REF must be in spec (because RUN and PWML are internally powered by REF). These are things to look for if you still get no PWML at all.

    Be aware that PWML may be difficult to trigger on since it will be 1~2us wide out of 10s or 100's of milliseconds UVLO cycling.
    Also, Table 3 (page 35) lists 5 faults that can prevent any PWML occurring, since they are checked once at the peak of VDD reaching 17.5V.  If any of these 5 faults are true, it goes into UVLO reset mode and just runs down VDD to 10V to cycle through again (until the fault is cleared).

    Note: RDM and RTZ shorts/opens are not literal zero/infinity values, but shorts are resistances < ~20K and opens are resistances > ~1Meg, or so. 
    I'm not sure of the exact values, but values extreme enough to not be useful for almost any conceivable application of this controller.  
    Your schematic values are comfortably within these limits, but it's possible the pcb components or connections could be wrong somehow.

    Regards,
    Ulrich

  • Ulrich

    thnx for heads up on this.

    will double-check for sure.

    Diode D1 is being changed to the correct type ALTHOUGH NOT FOOTPRINT YET.

    Let us see how this works out.

    ROBIN