BQ76930: Request a Design review

Hi Louis,

Here is my feedback below:

• Pins 11 and 12 should connect to CAP2. They are not truly no-connect pins. 
• The pullup resistors for SDA and SCL are very large. Normally, I would expect a value close to 10k.
• I did not see where the TS2 pin is tied to. I assume it will connect to a thermistor. In some reference designs a 4700pF capacitor is used in parallel with the thermistor to help filter noise.
• The cell 1 voltage is being used to drive the TS1 pin (for booting the device). This will work, but it will load this cell. Normally, you want to control this pin with an MCU or a button. There is an app note that discusses different options (https://www.ti.com/lit/an/slua769/slua769.pdf) or this reference design (TIDA-01093 https://www.ti.com/lit/ug/tiduc43a/tiduc43a.pdf) is a good example.
• We recommend using individual gate resistors when using multiple FETs in parallel. These app notes are good references: https://www.ti.com/lit/an/slua773/slua773.pdf , https://www.ti.com/lit/an/slva729a/slva729a.pdf

Best regards,

Matt