Hi Aaron,

Please upload your waveform again, it is not show up.

Thanks, Aaron.

Can you please add SW in the picture? and schematic?

HI  Chasel

Due to confidentiality , I cannot publish the schematic on E2E

I can send you the schematic through email

Hi Aaron,

I've sent you the request, we can start a thread from there.

In terms of the waveform you provided, both switching node did not pull-in when load steps up, we need to check schematic for sure.

Thanks

Chasel

Hi Aaron,

Schematic is well-received, can you try enable USR? change USR threshold to 60mV.

Hi Chasel

USR  to 60mV

No obvious improvement

Thanks, Aaron.

May I know what is the OCP setting now? and the test result of OCP?

Is there any chance that remote sense resistor not installed but only local sense?

Hi Chasel 

May I know what is the OCP setting now?

=>30k

and the test result of OCP?

=>pass Iout 64A  OCP

Is there any chance that remote sense resistor not installed but only local sense?

=>Have remote sense resistor

1.I have checked the layout copper is no problem

2.Check the quantity and value of output capacitor(MLCC 10u 1u .....) is intel's recommendation

Hi Aaron,

Can you please add 0.22uF at C1447 and C1453 to see if there is any difference?

Thanks

HI Chasel

1.I left a message for the first time, I adjusted Csense and it improved slightly,

2.Adjusting RAMP voltage also improved, but the jitter became too big

3.Is there a jitter limit for D-cap+TM Control?

4.The test result is closely related to the valley value of the inductor current

0As long as the inductor current valley is greater than 0A or above, the droop will be much better

Is the TPS53626 light load to heavy load characteristic like this?

Can you please add 0.22uF at C1447 and C1453 to see if there is any difference?

=>Is adding 0.22u too big?

Hi Aaron,

Happy Mid-Autumn Festival.

1.I left a message for the first time, I adjusted Csense and it improved slightly,

Did you try 0.22uF yet?

2.Adjusting RAMP voltage also improved, but the jitter became too big

Lower RAMP should help too

3.Is there a jitter limit for D-cap+TM Control?

No, as long as you did not see minimum-off time pulse during steady static, it is stable even jitter is a little heavy.

4.The test result is closely related to the valley value of the inductor current

0As long as the inductor current valley is greater than 0A or above, the droop will be much better

Is the TPS53626 light load to heavy load characteristic like this?

No... it is not related to the current level, despite of load step, the switching node did not fire intensively, can you try to increase the load step to see if there is any difference?

Can you please add 0.22uF at C1447 and C1453 to see if there is any difference?

=>Is adding 0.22u too big? No, it is not.

HI Chasel

Happy Mid-Autumn Festival

1.I left a message for the first time, I adjusted Csense and it improved slightly,

Did you try 0.22uF yet?

=>No, I didn't try 0.22u, I only tried 0.022u, 0.047, 0.068, 0.1u, but I think 0.22U to much.

Generally Csense*REQ is slightly larger than L/DCR
If in C1447, C1453 0.22u
Add the original C113 C118 0.22u to a total of 0.44u
I check C113 C118 is  0.22u
Csense*REQ is 2.2 times greater than L/DCR
I will try C1447, C1453 0.22u

2.Lower RAMP should help too

=>Yes, it is correct, the test result matches

3.No, as long as you did not see minimum-off time pulse during steady static, it is stable even jitter is a little heavy.

=>I am glad to see this message thank you

4.No... it is not related to the current level, despite of load step, the switching node did not fire intensively, can you try to increase the load step to see if there is any difference?

=>Use tps53626 as the other power rail (0 load line),When load transient
 I saw that the switching node became denser, But this is the case in PVCCP, I wondered whether it was D-CAP+TM characteristic.
I will try the load step

Thanks, Aaron. I'll wait for your result.

HI Chasel

1.C1447, C1453 0.22u

a.The test result is no obvious improvement (figure 1)

b.Csense is to large  (figure 2)

2. increase the load step to see if there is any difference?

When load transient I saw that the switching node became denser  (figure 3)

Thanks, Aaron.

It looks SW pulses not expected, the expected pulses behavior shall be like figure35 and 36 in the datasheet.

Can you please share layout with me as well?

You have try

1. Compensation

2. RAMP.

3. Csense

4. USR.

but did not get too much improvement, so I would like to check layout as well.

How did you apply the load? via intel tool? or from e-load?

HI Chasel

1.layout I think the risk is very low, because there is no problem with TI check

2.Not intel tool or e-load

3.I choose RAMP to adjust to improve droop

Thank you

HI Chasel

Yes, I finally chose 60mV RAMP to improve droop

HI chasel

It looks SW pulses not expected, the expected pulses behavior shall be like figure35 and 36 in the datasheet.

Can you please share layout with me as well?

=>I think the current slope and current step are not large enough

In the previous experiment, increase the current load step，SW pulses denser is more obvious

1.After adjusting RAMP, SW jitter is 40%, but steady state not see minimum-off time pulse, is there any risk?

Hi Aaron,

Thanks for the update, can you please show me the waveform here? If you did not find minimum-off time pulse or two consecutive pulses in one duty cycle, that is stable.

HI chasel

As attached