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TPSM846C24: Please validate my schematic design.

yuichi shintomi
Intellectual 315 points
Part Number: TPSM846C24

Hi Team.

I designed the schematic of the FPGA core power supply with the TPSM846C24. I have inserted the material, so please check it. What I care about is that I want to know if there are any problems with FPGA decoupling (MLCC). Thank you.

Sep_23_2020_TPSM846C24_0.95V_15A_Design_Shintomi.pdf

Regards,

Yuichi Shintomi

  • 0
    TI__Guru 56825 points

      Yuishi Shintomi,

    I don't see anything wrong with the design.  WeBench is pretty good with identifying those for you.

    However, you mentioned concerns about FPGA decoupling with Mult-layer Cerramic Capacitors (MLCCs)

    Are you including them in your output capacitors listed in WeBench, or are you asking about additional external MLCCs local to the FPGA you will be powering with this circuit?

    If you are concerned about capacitors not on the schematic, I would need to know what kind and how many ceramic decoupling capacitors you have.

    In addition, is the power supply located right next to the FPGA, or is it routed from a few tens of millimeters (or longer) away?

  • 0 in reply to Peter James Miller
    Intellectual 315 points

    Hi Peter,

    Thank you for your kind reply. I care about “additional external MLCCs local to the FPGA”. MLCCs are on the right side of the blue dashed line in the circuit diagram inserted in this reply and in red on the BOM. These are not included in the WEBENCH report. MLCCs will be separated by about 25mm.

    Sep_24_2020_TPSM846C24_0.95V_15A_Design_Shintomi.pdf

    Regard,

    Yuichi

  • 0 in reply to yuichi shintomi
    TI__Guru 56825 points

     Yuichi,

    Adding 944uF of capacitance to the existing 1,128uF could negatively affect the stability of the loop as it will shift the LC resonance and cross-over frequency down, which will reduce phase margin and stability.

    You could update the WebEx design to better approximare the design you are using, adding an additional 470uF electrolytic capacitor to account for the 330uF bypass at the load, and 12 additional 47uF capacitors to approximate the 5x 100uF and 2x 47uF.  That will allow you to adjust the compensation design to account for the added capacitance.

    As an approximation, the added output capacitance will reduce the L-C resonance by about 1/3, you could increase Ccomp3 (VSDIFFO to FB capacitor) by 50% (to 1.5nF) to reduce the zero frequency by 1/3 to compensate.  You will want to also reduce Rcomp2 (resistor in series with Ccomp3) to maintain their product and keep the high-frequency pole frequency approximately the same (576-Ohms).

  • 0 in reply to Peter James Miller
    Intellectual 315 points

    Hi Peter-san,

    Thank you for your excellent advice!. I have fixed the Schematic according to your advice. I ran a simulation with WEBENCH and was able to secure a phase margin.

    Sep_25_2020_TPSM846C24_0.95V_15A_Design_Shintomi.pdf

    If you have any other concerns, please comment. Thank you.

    Regards,

    Yuichi

  • 0 in reply to yuichi shintomi
    TI__Genius 14455 points

    Hi Yuichi-san

        Peter is out today and will get back to you with any feedback on Monday. If you have taken care of the inputs that Peter gave, that should be good.

    regards,

    Gerold

  • 0 in reply to yuichi shintomi
    TI__Guru 56825 points

      Yuichi,

    Glad we could help, and that you were able to adjust the compensation in WeBench to secure the required phase boost for a stable design.  It looks pretty good now.  Please let us know if there is anything more we can do to assist you.

  • 0 in reply to Peter James Miller
    Intellectual 315 points

    Hi Peter-san,

    Thank you for your kind reply. I think Schematic is complete. I was relieved. Let me ask you one question. About "Rsense1 & 2" resistors.

    I designed it with Rsense = 51ohm specified by WEBENCH. What is the purpose and meaning of this value?

    Regards,

    Yuichi

  • 0 in reply to yuichi shintomi
    TI__Guru 56825 points

     Yuichi,

    RSNS1 and RSNS2 are node breaking resistors in the remote sense path.  They provide a separation between the output voltage and ground nodes and the remote sense nodes.  This ensures that the remote sense node does not accidentally become shorted to the output voltage or ground node at some point other than the load, which would affect the remote sense function's ability to compensate for losses in the power delivery path.

    The resistors also limit the current that can be draw from the remote sense input pins in the event that the output voltage is forced negative due to heavy load during shut-off.  If a differential filter will be used by placing a small capacitor between the VS+ and VS- pins, these resistors will form a filter pole to keep very high frequency noise out of the remote sense path.  Finally, these resistors can be used for injecting a small AC signal from a network analyzer to measure the frequency response of the converter and generate a BODE plot.

    They could be 10-ohms or 100-ohms, but 51 ohms is most commonly selected to impedance match the injection to a 50-ohm coaxial cable.

  • 0 in reply to Peter James Miller
    Intellectual 315 points

    Hi Peter-san,

    Thank you for giving me a kind lecture. had imagined short circuit protection, but I couldn't think of any other noise, shutdown, negative output. I was able to learn very much. Thank you very much.

    The Schematic check will be completed. Thank you for your cooperation while you are busy.

    Regards,

    Yuichi

  • 0 in reply to yuichi shintomi
    TI__Guru 56825 points

     Yuichi,

    I am glad I was able to help.  Let us know if you need any other assistance by creating a new threat.