BQ76942: cell balancing not working

Hi,

thank you for your quick answer.

Do you already know the exact date, when the IC will be available? We plan to introduce our device in 1Q2021 with an anual quantity of 100.000 pieces.
Furthermore, is it possible to get samples of the final IC for testing? Otherwise we might have to look for alternative ICs

Best regards,
Tobias

Hi David,

we would try the BQ76952 then, how should we order the samples to be sure to get the final version.

Could you check if my configuration is correct for the automatic balancing then.
Are the problems I descriebed fixed in the final version or did I misunderstand the documentation?
And how will the SubCmd CB_ACTIVE_CELL (0x0083) will behave in the final version ? Is it 2 bytes then?

Best regards,
Tobias

Hallo Tobias,
We plan to RTM BQ76952 next week. I suggest you create a notification on the BQ76952 product page. At RTM, when it becomes "ACTIVE" (from "PREVIEW"), you will be able to order the final samples. 

I'll loop a colleague for your other question.

Have a nice week-end!

Hi,

thanks I found the updated datasheet and changed the addresses.

The chip should have been released last week, when does it happen?

Best regards

Tobias

hi,

the new samples arrived but I’m still unable to perform balancing.

I adjusted the subcommand addresses according to the new reference manual.

When I use the same settings (cell configuration is adjusted according to ref man) automatic balancing does not start. When I try to start it manually with (0x0083 CB_ACTIVE_CELLS()) the written bit-pattern, when read back it was reset to 0.

So, I thought maybe my checksum is wrong. I calculated it according to p.15 in the reference manual:

“The checksum is the 8-bit sum of the subcommand bytes (0x3E and 0x3F) plus the number of bytes used in the transfer buffer, then the result is bitwise inverted. “

I understand that for example subcmd 0x0083 with data 0x8000 uses 2 bytes in the transfer buffer, which means checksum = ~(0x83 + 0x00 + 2) = 0x7A (calculated in an uint8_t variable). And the length is 6 (including subcmd-, data-, length- and checksum-bytes).

When I look into the code example in https://www.ti.com/lit/zip/sluc701 it seems that the checksum is calculated like when reading a subcommand :

“The checksum is calculated over 0x3E, 0x3F, and the buffer data, it does not include the checksum or length in 0x60 and 0x61.”

When I use this checksum calculation the data is saved into the register, nevertheless it does not start balancing on that specified cell. But the command (0x0084 CB_SET_LVL()) doesn’t work anymore.

So, I conducted some testing CB_SET_LVL() works with checksum calculated with ( 0x3E, 0x3F and the length of the buffer (2)) or with ( 0x3E, 0x3F and the length of the buffer +4 (6)). It doesn’t work with checksum calculated with (0x3E, 0x3F, and the buffer data). This command behaves different in another case, too: when I write the subcommand to 0x3E, 0x3F and read it back I get first 0xFFFF (like with every other cmd) but then I get 0x0000 instead of the 0x0084 ?!?

Whereas CB_ACTIVE_CELLS() only works with checksum calculated with (0x3E, 0x3F, and the buffer data).

Another question of mine is that in the code example in https://www.ti.com/lit/zip/sluc701 data is send to 0x40 register without first read back (0x3E, 0x3F) multiple times and wait until the transfer register is loaded.

Bottom line is:

• I cannot balance, whether host controlled nor automatic.
• CB_ACTIVE_CELLS() and CB_SET_LVL() behave different.
• I do not know which calculation for the checksum I should use.
• Can I write directly into 0x40 without first read back (0x3E, 0x3F)?

best regards,
tobias

Hi Tobias,

Are you able to write other sub-commands?

Hi,

yes I can. For example the SECURITY_KEYS.

Thanks , I found out that the registers that are marked as write-only behave like (0x0084 CB_SET_LVL()). That makes sense, but is there no chance to read back the register to be sure that writing was successful?

So can you confirm that the bit-inverted sum over the command bytes and the values of all data bytes is the right calculation for all reads and writes.

I recommend to change the sentence at p.15, "... sum of the subcommand bytes (0x3E and 0x3F) plus the number of bytes used in the transfer buffer ...", because "the number of bytes"  will be interpreted as length.

Can you answer the following questions:

• Why doesn't balancing start automatically?
• Why doesn't it start when writing CB_ACTIVE_CELLS()?
• Can I check if write-only register were written correctly?
• Can I write directly into 0x40 without first read back (0x3E, 0x3F)?

best regards,
tobias

Balancing does not start automatically because the default configuration does not have balancing enabled. ...

In my initial post I described my configuration:

Tobias Schwering said:

First I set the following registers for initialisation:

1. 1. I enter the Config Update mode,
   2. initalize the used cells in Vcell Mode: 4 cells at cell 0,7, 8, 9 (addr: 0x92EA -> data: 0b 0000 0011 1000 0001, LSByte first)
      -> could be problematic as datasheet states that at least cell 0, 1 and 9 should be connected -> will be changed in next hardware revision
   3. set the balancing config: do balancing when relax, sleep and while charging (addr: 0x931A -> data: 0b 0000 0111)
   4. set the DA config : use internal temperature for FET-temp and cell-temp and use milliamps and millivolts (addr: 0x92E9 -> data: 0b 0001 1001)
      -> no external termistor is connected, when I read the DASTATUS5 later Cell- and FET- temperature is still at ~214K but Internal temp is ~310k
   5. set the CB_SET_LVL to 3900 mV (addr: 0x0084 -> data: 3900, LSByte first)
      -> this subCommand has some different behavour: when SubCmd is written to 0x3E, 0x3F and re-read it does say 0x00 0x00 (after 0xff 0xff) instead of the SubCmd
   6. set the gain for current and capacity sensing
   7. exit the Config Update mode
   8. disable sleep mode

In the first post you answered to, I wrote:

Tobias Schwering said:

"I adjusted the subcommand addresses according to the new reference manual.

When I use the same settings (cell configuration is adjusted according to ref man) automatic balancing does not start. When I try to start it manually with (0x0083 CB_ACTIVE_CELLS()) the written bit-pattern, when read back it was reset to 0."

The value I adjusted the Cell Config to is :0b1100000000000011 -> the upper and lower two cells.
Aditionally I added a dummy resistor to TS2, and configured TS2 to Cell temp and TS1 to unused.

When I double checked the configuration with the Battery Management Studio, I found that I wrote the Cell Configuration to the wrong address, thats why the balancing couln't work.
Host controlled balancing does work now. However automatic balancing is not.

Could you please take a look into my configuration, to see if something is blocking the automatic balancing?

And the Configurations :

WM5295 said:

Can I write directly into 0x40 without first read back (0x3E, 0x3F)?

You can write to 0x40, but anything written will be lost when you write the command to 0x3E and 0x3F.  Even if the sub command does not replace data the mechanism or syntax to send a command with data does not have a method to include the subcommand and data separately.  Send the sub command and data together then send the checksum and length as described in 3.1 of the TRM"

-> that was exactly what I meant. In the TRM is not clearly stated that there is that difference between the write and read commands for subcommands.
when you read it, you need to write the subcmd to (0x3E, 0x3F). Than read these two registers until they answer the original subcmd. -> That is what I meant with read back (0x3E, 0x3F).

Thank you for clarifying that.

best regards,
tobias