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TPS659037: TPS659037 when used on AM571x Development Kit Evaluation Module

high speed guy
Expert 3505 points
Part Number: TPS659037
Other Parts Discussed in Thread: AM5718

HI,

I am using the AM571x IDK EVM (Part #TMDXIDK571x) which has a push-button switch connecting to PWRON Pin of the TPS6590379 PMIC to power-up the board. However I need to be able to power-up my design as soon as input power (5VDC to VCC1 Pin C7 of the TPS6590379) is available. Would you let me know how to achieve this?  In other words what should I do with PWRON C11 Pin to ensure always power up as soon as supply is provided to pin C7.

Thank you, 

HSG 

  • 0
    TI__Genius 10000 points

    Hi HSG,

    if you don't need a push-button, you can leave PWRON floating. Then, use POWERHOLD (GPIO_7) to enable the device. If you want to turn on when power is available, you can pull POWERHOLD to LDOVRTC. One important note here is that this will not allow a sequenced power down, you will only be able to power off by a loss of supply to the PMIC.

    If you have a power good pin available from the pre-regulator, you can also use that as the enable for the PMIC on POWERHOLD. That may help allow for a sequenced power down before the supply is removed.

    User guide for further details on the PWRON/POWERHOLD options: https://www.ti.com/lit/pdf/sliu011

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    TI__Expert 3505 points

    Hi Nastasha,

    Thank you for your helpful information.   A few more related questions:

     I will pull-up POWERHOLD (GPIO_7) to LDOVRTC to turn on the PMIC when power is available.

    1. With POWERHOLD (GPIO_7) pull-up to LDOVRTC, I will need to remove power to turn off the PMIC. Are there things I need to do to ensure the PMIC and AM5718 are OK (sequence down properly) when input power is cut off because pulling-up POWERHOLD (GPIO_7) to LDOVRTC does not allow a sequenced power down?  Note I see  a brief discussion on using page 182 of the AM5718 data sheet and discussion of the PORZ on the PMIC.   Can you explain further?
    2. Does BOOT1 pin need to be pull-up to LDOVRTC for POWERHOLD (GPIO_7) to be pull-up to LDOVRTC as well?
    3. What are the functions of BOOT1 pin when it is grounded and when it is pull-up to LDOVRTC?

    Thank you,

    HSG

  • 0 in reply to high speed guy
    TI__Genius 10000 points

    Hi HSG,

    Below is some feedback on your questions:

    1. If POWERHOLD is pulled up to VRTC, all the rails will shutoff at the same time when the UVLO is detected. Since the digital rails will go low faster than the power rails, it is possible that the PORz condition can be met, but it needs to be tested on the system since there is schematic and layout dependencies.

    Also, it is important to understand the risk to the PMIC by removing power while load is present. Please see section 6.2.2.7 in the datasheet that includes design risks for shutdowns through loss of power events. There is risk of damaging the PMIC if not meeting our layout recommendations.

    2. BOOT1 can be pulled up to VRTC.

    3. BOOT1 should be pulled up high if you are using the warm reset function (nRESWARM) of the PMIC. When pulled high, the RESET_OUT pin will toggle during a warm reset. This toggle is required by the processor to execute a warm reset correctly. If you are not using the warm reset function, this pin can be grounded.

    Thanks,

    Nastasha