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UCC28704: Calculation of the transformer

Part Number: UCC28704

Dear team.

Please teach me whether the following calculation right.

VIN=AC100V, VOUT=7V/5W

Dmax is about 40% by Nps=10=(Dmax) x 90Vdc/ (0.475x(7+0.5)) expression.
As Dmax is around 48%, according to the calculating formula of the datasheet, I think the frequency not to reach around 78kHz.

Lp = 2 x 7 x 0.7/(0.85xIpxIpx78kHz) -> Ip=0.25A
Therefore, I connect resistance less than 2.8Ω as the current detection resistance is 0.72V/0.25A=2.88Ω.
As the saturated current of the trance becomes 0.4A, 1.8Ω or more, it is less than 2.88Ω.

Regards,
PAN-M

  • Hello Pan-M,

     

    Thank you for your interest in the UCC28704 flyback controller.

     

    Your Nps equation already has a predetermined turns-ratio, and the Lp equation implies that Lp = 2.36mH.  However there is no information about how you arrived at these numbers.

     

    There are several steps in the design procedure that are not shown in your posting.
    This implies to me that you already have a transformer design and you may be trying to make it work in the 7V/5W application.

     

    The best design method is to follow the design procedure in the datasheet in the order that it is presented. The UCC28704 Excel Design Calculator tool also does this: https://www.ti.com/lit/zip/sluc603

     

    If you already have a transformer to use, then with this calculator you can adjust your inputs to result in the inductance and turns-ratios to match the existing transformer. Then decide if the input variable values (min/max voltages, currents, frequency) needed to achieve that transformer design are acceptable.

    If acceptable, you can proceed to determine the other component values needed for your design.  
    If not acceptable, then one or more parameters of the transformer must be changed.

     

    Regards,
    Ulrich

  • Thank you for reply, Ulrich.

    I was input the value of the transformer that I wanted to use for a spreadsheet.
    Would you please check this value?

    Copy of sluc603b.xlsx

    Regards,
    PAN-M

  • Hello Pan-M,

     

    In order to make the design work with the transformer parameters you provided in the calculator tool, I have revised the values of cells: B13, D21, and C46.

     

    Copy2 of sluc603b.xlsx

    Here are the reasons for this:

     

    1. Because you require Lpm = 2.30mH, I had to reduce the maximum full-power switching frequency to 51kHz to make the calculator recommend Lpm = 2.30mH.

    2. Because your require Nps = 10, I had to increase the minimum RMS input voltage to 94Vrms to make the calculator recommend the Nps ratio = 10. (Don’t worry, we’ll get back to 85Vrms later.)

    3. Because your require Nas = 1.6, I had to increase the “output voltage at initial turn-on” to 4.89V to make the calculator recommend the Nas ratio = 1.6.

      For item 1, Ipk_sec and Ipk_pri are already predefined by the output current and the Dmag duty cycle. They can’t be changed. So, from the P = ½*Lpm*Ipk^2*fsw equation, fsw has to reduce to allow Lpm to increase.

      For item 2,

      This calculator assumes a bulk ripple voltage of 40% of the peak, so the minimum bulk valley is assumed to be 60% of the minimum input peak. For 85Vac input, this minimum valley voltage = 85V *1.414*0.6 = 72Vmin. A transformer with Nps=10 will not work at his low valley voltage; there is not enough duty cycle. So there would be line-frequency ripple in Vout at full load, 85Vac.

      To make Nps=10 work, a lower bulk ripple voltage is needed, with a higher min valley. 94Vrms delivers this condition. Using the assumed 0.6 factor, 94V*1.414*0.6 = 79.7Vmin. In order to allow 85Vrms input, the total bulk capacitance must be high enough to keep the minimum full-load ripple voltage to >80Vmin. For a 5-W output power, Cbulk > 12.4uF can do this. Since your input for Ca and Cb at cell C79 shows 10uF each, you already have a total of 20uF, which can easily keep the minimum ripple voltage high, AND account for -20% tolerance on the cap’s value.

      So although 94Vrms is shown in cell B13, 20uF for Cbulk will allow your design to operate down to 85Vrms.

      For item 3,

      With an Nas turns-ratio of 1.6, the reflected voltage from secondary to auxiliary will be above 8V on VDD only when Vout > 4.89V. During start-up, while 0V < Vout < 4.89V, primary VDD must stay above 8V by drawing down the charge stored in the Cvdd cap. If Cvdd is too small and VDD falls <8V before Vout reaches 4.89V, then the controller will shut off and attempt to restart over and over again.

      You may need to make a trade-off here. There are 4 parameters that you specify, but only 1 of them can be true; not all four.

    1. Vout at turn on = 2V (cell C46)

    2. Cvdd = 0.33uF (cell C100)

    3. Start-up time < 0.9s (cell C96)

    4. No-load input power < 30mW (cell D17)

      These are all interrelated with item 3.
      If you must have constant current (CC) operation down to 2V on the output, then you cannot have Nas = 1.6. The transformer must be redesigned.  If you can allow the power supply to shut off when Vout falls < 4.9V during CC operation, then you can use this transformer.

      To allow the controller to start, Cvdd will probably have to be larger than 0.33uF. Cvdd has to hold up the controller while VDD is falling from 21V down to 8V. During this time, Vout is being charge at the max CC rate, but Cout is specified as 940uF (cell C115). That is a lot of charge to deliver to get Vout > 4.9V, assuming no output load applied. If a load is applied during start-up, the start-up time is even longer. So Cvdd must be big enough to carry VDD until Vout > 4.9V. This may mean several uF, instead of only 0.33uF.

      But your choice of trickle charge resistance Rt = 15.3Meg (cell C92) is based on achieving low stand-by power (presumably at 230Vac) , and Cvdd = 0.33uF is based on 0.9s start-up time. If Cvdd must be several uF, then you will not be able to achieve start-up in <1s. If you reduce Rt to get back to 0.9s, you will not be able to achieve <30mW stand-by power.

      You can reduce Cout if you don’t really need that much capacitance; that will help keep Cvdd lower.

      But the simplest trade-off is to allow longer start-up time, to preserve Pstby < 30mW. If start-up time is more important than Pstby, you can reduce Rt.

      This is the way I see it, for your design.

      Regards,
      Ulrich

       

  • Thank you, Ulrich.

    1. The frequency becomes slow, but I think that the inductance level does not have any problem.
    2. As for the winding ratio, there is the concern on the low input voltage side, but I think that I do not have any problem at 10:1 as it seems to be adjustable by input capacitor.
    3. As the output voltage became 11V in rating as for the vice-winding, I thought that it should lower the capacity of the output capacitor to shorten boot-time as much as possible.
        When I am worried about the ripple voltage of the output, I think that it put a small inductor in the output side would be good.

    Regards,
    PAN-M

  • Okay, PAN-M,

    It sounds like you understand the issues.

    I will close this thread.

    Regards,

    Ulrich