• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 244 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65094: TPS65094 design review

user4930826
Prodigy 10 points
Part Number: TPS65094

Hello,

Please help me to review the TPS65094X SCH with Apollo Lake in attachment, thanks.

I have other two questions:

1 CPU have VCGI and VNN feedback, which feedback TPS65094 should connect, CPU's feedback or VR's output?

2 Can I change the VDDQ's(BUCK6) voltage except for changing IC like Table3-1 in datsheet?

PMU_TPS65094X.pdf

  • 0
    TI__Genius 17380 points

    Hello,

    For a schematic review - please complete the TPS65094x Schematic Checklist and re-attach it with any questions / concerns. I will perform a second review once you provide the completed form.

    1. Generally both - typically the Intel reference design (IBL# 560683) is followed. In that, the feedback is connected to the CPU directly but with a 100 ohm connection to the output capacitors of the VR. When the CPU is installed, the voltage at the CPU is dominant. If the CPU is missing, then the VR will still work through the 100 ohm connection with minimal impact (since it is much smaller resistance than the FB pin input impedance).

    2. The default voltage can only be changed by changing ICs, however the voltage is adjustable by I2C in the volatile memory registers after power-up. It will reset each time the PMIC resets so software would need to rewrite it each time the software loads.