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WEBENCH® Tools/LM25088: lm25088 webench design over current

Part Number: LM25088

Tool/software: WEBENCH® Design Tools

I used WEbench to design +12vto -18volts supply.

I have many problems:

1-with a 009 rs resistor the maximum currentLM25088-2_12V_TO_-18V_2A.pdf is around 1.25 A instead of 2 , but with my personnel calculation a 0.011mohm should be ok.

 if I disable de HICCUP mode, by shorting Cramp capacitor , i can reach mode dans 4 A , in fact de current limiter look disable ALSO.

2-But the big issue is the current sink from 12 volt start at 3.9 Amp for a -18volt output current of 2 ( 77% eff) AND reached over 7 Amp after many second

that look like a device going to latch up and short...

also in my design I add a big 150uf polymer, if i do not used it , I have a lot of noise at the output

LM25088-2_12V_TO_-18V_2A.pdf

in include my design, the only difference is I used a -2 device instead of -1 device. 

  • Hello Marc, 

    Let me loop in the Apps engineers covering this device. 

    Cheers, 
    Denislav

  • Hi Marc,

    Please send the PCB layout for review. In particular, check that the cap from VIN to -VOUT is placed close to the FET/diode/sunt as this forms the switching loop for an inverting buck-boost (IBB) configuration.

    Note that the inductor current for an IBB is effectively Iin + Iout, and this current flows in the shunt resistor that determines current limit.

    Also, the RAMP capacitor should not be shorted as this is required to set the upslope for emulated peak current-mode control.

    Regards,

    Tim 

  • Ħi this is the layout :  for the ramp capacitor , after i short it i had no more current limite in fact, but in spec we can read " The hiccup mode can be completely disabled by connecting the RES pin to GND. In this configuration, the cycle-by-cycle protection will limit the output current indefinitely and no hiccup sequence will occur" in spec page 18. ALSO  I put an -2 version on board instead of -1 : this can generated ALL my problemes ?texas_support_lm25088.pdf

  • Hi Marc,

    The key capacitor is C67 - this should be placed closed to the FET to minimize the switching loop area comprising the FET, diode and sense resistor. The lower parasitic inductance improves the performance of the circuit, allowing reduction of the 1100pF snubber capacitance (which is quite high, especially at this switching frequency).

    Also, please measure the voltage on the sense resistor near current limit to see if it corresponds to the current limit threshold of 120mV as expected.

    Regards,

    Tim