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TPS62130A: Questions for minimum on time and phase glitch

Part Number: TPS62130A

Hi,

I would like to double confirm 2 questions below.

1. Current design is with 2.5MHz Fsw for 12V to 1V conversion.

As datasheet mentioned, the minimum on time is 80nS, but we got 60nS, is it within the spec?

And it looks the Fsw is limited to 1.58MHz.

2. There is glitch at rising edge of phase, is it due to miller effect?

Thanks and Best regards,

Tiger

  • Tiger,

    1. Yes, the 60ns is within spec for the minimum on time.

    1a. While in Power Save mode, the tps62130A will reduce the switching frequency proportional to load to maintain the output voltage regulation and improve efficiency (please see figures #24-31 in the datasheet). 

    2. Yes, this is caused by the additional Miller effect loading on the internal gate driver circuitry.

    Sincerely,

    -Matt