Other Parts Discussed in Thread: SN74LVC1G125
Hello,
We are implementing a power supply based around TPS54561 and we are looking for some clarification regarding the external synchronization..
Datasheet, 7.3.12, states:
"The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in Figure 37. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V and have a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed such that the default frequency set resistor is connected from the RT/CLK pin to the ground when the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor (that is, 50 Ω) as shown in Figure 37. The two resistors in series provide the default frequency setting resistance when the signal source is turned off. The sum of the resistance should set the switching frequency close to the external CLK frequency. AC coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended."
We plan to drive this pin with a tristate buffer, SN74LVC1G125 that we enable only when a valid sync signal is present. Is our understanding then correct that we can drive the pin as Hi-Z Clock Source since the buffer will be Hi-Z until we enable the sync and there from it will be compliant with the drive signal requirement? Or are there other issues that we should keep in mind and drive the pin as if it is a low-Z source?
Regards,
Magnus
