TPS56121: TPS56121 design noise

david sun1

Part Number: TPS56121
Other Parts Discussed in Thread: TPS56221

Dear Power Design Expert,

I have a design with TPS56121. the parameters are from Webench, it is a 12V input, 9V, 9A output.

it is used to drive a TEC, the R125 will be set to 2.8V or 0.48V to control the output voltage to 1.6v or 8.5V.

the board is 4 layers. one full ground layer. The board can output the correct voltage and current without a problem, but for some reason, it causes the system overall noise level to rise. after some measurement, I notice that the input cap has very high transaction noise as in the following waveform. I attached the waveform, schematic, and layout. for this kind of problem, is there a general rule to troubleshoot. for example, is the components value, placement, layout trace should be paid attention, how to design the next test to improve the design? where should I start to respin the board?

high current power regulator is not easy to design. hope I can get some suggestion, appreciate your help.

The high lighted area is the 12V input to the U56

over 4 years ago

0 David_Daniels over 4 years ago

TI__Mastermind 21210 points

The input current to the dc dc converter is a pulse current see Q1 current

To reduce input ripple, you can add a bulk capacitance (>100uF) and add a ferrite bead (similar to BLM18SN220TN1D) in

series with 12V source to the input of the dc/dc converter.

0 david sun1 over 4 years ago in reply to David_Daniels

Intellectual 280 points

Hi, David_Daniels

Thank you for your prompt response, for some reason, I couldn't see the file in your reply, could you please send the file again.

David Sun

0 david sun1 over 4 years ago in reply to David_Daniels

Intellectual 280 points

Hi David,

I think the input ripple is OK, depend on how we define the ripple, I am targeting the ringing at the beginning of each transient. if I assume there is not ring, then the input ripple(yellow trace) should be defined by the two white lines. what I concerned about is the ring amplitude, which is defined by the two red lines.

I will see how the extra Capacitors will affect the ripple and the ring. I just want to make sure we are targeting the same issue.

0 David_Daniels over 4 years ago in reply to david sun1

TI__Mastermind 21210 points

Maybe this link works

0 david sun1 over 4 years ago in reply to David_Daniels

Intellectual 280 points

Hi David,

I got the file this time, it is very helpful. by the way, I found a very interesting article on the web.

in the file, it mentioned that R117, C84, R124, C93 in the design( schematic in the top post)are used to reduce the ring of the switch. all the value of these components are from Webench, is there any extra information can be provided to optimize the performance of the ring compression.

if increasing R117, or reduce the C84 and compress the ring, what is the trade-off for the FET losses?