UCC28780: ucc28780-PROTO3 occasional RUN

robin gangopadhya18

Mastermind 6306 points

Part Number: UCC28780

Ulrich:

On proto3 for which we are reporting results as of Monday, as we said, we have sws, hvg, ref as expected. No RUN.

I pulled up CS pin by 24k which gives a bias of approix .3v at CS.

We started getting occasional RUN pulses. from about 100V

I captured 1 such. Pl see attached. That is at 175V VBULK.

The question is there must be something else missing here.

What would cause RUN to be so rare?

Any help will be highly appreciated.PRTO3_PULLUP_RUN1.pptx

over 5 years ago

0 Mike O' over 5 years ago

TI__Guru* 86286 points

Hello Robin,

Please consolidate threads with the issues you are working out with Uli.

Regards,

0 Ulrich Goerke over 5 years ago in reply to Mike O'

TI__Mastermind 40580 points

Hello Robin,

I agree with Mike that we should consolidate the various threads on this project, but try to solve one issue at a time, rather than several at once, since they may be interrelated.

From the "PRTO3_PULLUP_RUN1" file, I presume the Red trace is RUN and Blue is REF (they are unidentified). RUN, here is almost 100ms long and to me that is a level, not a pulse. To me pulses are a few us wide. PWML and PWMH will be pulses. RUN may be a pulse at very light loads, but during start-up it should be a level. Sorry about the semantics, but I'm trying to avoid confusion from different interpretations of terms.

Anyway, you captured a RUN signal seen in the file. Some observations I have are that the RUN and REF duration is much shorter than the REF-only durations. I am guessing this comes about because, when RUN is high, PWML is likely to be driven, maybe even PWMH, and when switching is active, VDD is loaded more heavily so Cvdd discharges faster. Since it is not sustained, I guess that the output is not coming up to maintain VDD.
In the cases where RUN is not seen, VDD is more lightly loaded and Cvdd discharges more slowly. That's what I guess, anyway.

I suggest that you check VDD and PWML with additional scope traces, if you are able to, to see what's happening when RUN is high.

Also, I see from the scope picture that sample resolution is 1MS over a 2-second sweep. That is 2us/point for single trace, or 4us/point for 2 traces.
It is possible that you may be missing some brief RUN pulses due to low sample resolution. Please increase your sampling.

Also, if I figure the scope out correctly, you are triggering at 0V on trace B (RUN) in Auto mode, which could miss a lot of short RUN's that might be happening. I suggest to trigger on RUN in Normal mode at ~2V level (with the higher sampling resolution) to capture any brief RUNs. Then you can investigate why the RUN is not sustained.

Next, I don't understand why you have a 24K pull-up on CS. You should not need a 0.3V bias on CS. In fact, this bias may be interfering with proper operation, since the initial start mode threshold on CS is 0.28V and 0.3V exceeds that.
Also, I see from your 09-09-2020 schematic that you have 330pF+390pF on the CS pin. With R30 = 1.5K this makes it a ~1us time constant which is a 1us delay to the real current sense signal. Once you get past the first few start-up pulses, this can allow huge current peaks due to the sensing delay.
Normally, Ccs is around 10~22 pF. It can be made bigger as long as the time delay is accounted for, but 1us is much too long.

Please remove that 24k pull-up and reduce your Ccs.
I suggest to add a few more probes to see what other signals are doing: VDD, PWML, CS, PWMH, Vout, etc. I know you may not be able to have all of them at the same time. You'll have to choose the next ones in the sequence. When RUN goes high, is PWML present? Does Vcs accurately reflect Vrs except with some noise and spike filtering, or is Vrs peak much higher than Vcs? Does Vout start to go up? Does PWMH work? Does Vout reach high enough to reflect back to Vaux and keep VDD above 10V?
When RUN is high, you don't need REF, because it is implied by RUN.

Regards,

Ulrich

0 robin gangopadhya18 over 5 years ago in reply to Ulrich Goerke

Mastermind 6306 points

Ulrich:

I thought I would separate each issue by " ask a related question" plus add a subject in the subject.

I would try to consolidate: to the extent, I understand the need to keep things wholesome & concise.

Also: Agree with the semantics. So I will use "level change" everywhere else when not related to PWMs.

That said, let me express appreciation for your patience & time to help through this tough situation we are in.

Now:

#1 All your points about traces are well understood. Let me see if I can get a 4 channel scope. The one 4ch we have won't store. Picoscope is 2 channel. But I get it.

#2 CS pin - the Debug document suggests if you do not get any switching or pulses, try pulling up CS pin to .3V, to reduce noise, add 330pF...so we did that because there was no RUN thus no PWML.

#3 Note that there was no RUN at all so far. Then reading the Debug Document, we first added 330pF...nothing happened. Then pulled up CS pin to .3V...we started seeing occasional RUN pin change levels ( 0 to 5V). The level change is occasional indeed. VREF level changes every time VDD goes below OFF level. This depends upon VDD capacitor as we can notice. We have 32 uF or so.

#4: Note that we also have reduced primary inductance following Debug Doc suggestion. It is right now approx 390 uH...With Rcs as .85 Ohm. This estimates 64V VBULK for PWML to start.

Seems I should instrument it better, make sure PWML goes through the isolation chain.

Would you think VDD level & HVG levels are acceptable or should they not be higher as in the Eval kit? What would make them higher?

Actions to take: remove 330pF from CS pin, remove pullup from CS pin. Retest for RUN & PWML with a more sensitive instrument.

Let me get started on all the above. Toughest will be 4ch scope to get today. Or even this week.

robin

0 Ulrich Goerke over 5 years ago in reply to robin gangopadhya18

TI__Mastermind 40580 points

Hi Robin,

I checked into the Debug Guide to look into the context of the 330pF and 0.3V offset on CS. I think it is a misunderstanding.
Section 7.1 suggest to add "UP TO" 330pF on CS, but then warns about the added delay. I concede that this is relatively vague advice.
Ccs should be as low as possible to do the job (which is to filter an inordinately large leading edge spike that tCSLEB can't blank out), and then accommodate by other means the delay that that cap value creates. It doesn't say how to accommodate it, however.

In your situation, you don't have any leading edge spikes to filter out yet (until you get PWML and can probe CS), so a huge cap there doesn't help.

In Section 6.1, the suggestion is to add an offset voltage to CS to allow it to reach 0.28V faster. Again, this is vague. We don't want to add an offset OF 0.28V (or 0.3V), we want to add a small offset (pedestal voltage) to reduce the remaining ramp time for Vcs to reach 0.28V. This is done for cases where the start-up Vbulk is low and xfmr inductance is high, so that di/dt is too low to allow Vcs to reach 0.28V within the 2-us start-up window. This 2-us limitation window is there to be able to detect a CS-shorted-to-GND condition and prevent further operation. A side-effect of this detection method is that low di/dt may be interpreted as a shorted-CS condition. Adding a pedestal to Vcs (like 50~150mV) can help reduce the ramp time to fall within the 2-us window to avoid the false "fault" shutdown. There is a practical limit to how much offset to add and still have sufficient L*I^2*fsw power to start, and to low-voltage start-up for a given inductance.

Again, in your situation, we need to assess the first few current pulses to see if an offset is needed. These depend on getting a PWML signal through the isolator to the FET first.

I'm not too worried about the exact values of VDDpk and HVG compared to the EVM board. There are tolerances on all parameters and your specific chip may be off nominal by a little bit. If the device puts out REF and RUN and even gets PWMLs, it is "happy" enough and you can get on to further power up of your board.

Regards,
Ulrich

0 robin gangopadhya18 over 5 years ago in reply to Ulrich Goerke

Mastermind 6306 points

Ulrich:

Points well made and I fully get it.

So we are removing the additional parts form CS....desperate: we were trying out all schemes, that are safe for the circuit to debug.

That is #1

#2 is an important realization: after succeeding with Depletion fet, VDD charge up, REF to 5V, my thinking has been RUN will go high at some level of VBULK. & nothing elese in the circuit determines RUN.

So far my thinking has been RUN is not related to external circuitry as long as CS circuit is consistent. Proof of that are in VDD, SWS & HVG & REF signals- and we have those consistently now.

AUX winding is fully connected to the controller: VS & its rectifier version as VDD.

Good thing is RUN signal only goes to Q4 gate- so either internally it is generated or 2N7002k gate is short( which it is not)...one should get RUN high.

But does RUN stay high if PWML did not kick off AUX voltage build?

Seems RUN needs secondary to be in circuit & loaded for it to change level & stay High..implying PWML is happening.....magnetizing current alone wont be sufficient to have CS signal to tell controller all is well & pull RUN high.

I think I will get 4 ch Tek scope capture today. It will be an iPhone picture...will see how it appears before I send these results.

thnx much.

robin

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UCC28780: ucc28780-PROTO3 occasional RUN