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TL3843: Designing a switchmode current limiter, power FET gets extremely hot

Part Number: TL3843

I'm trying to design an efficient switch-mode current limiter for a 24V supply. The idea that I've landed on is to use a TL3843DR-8 as a PWM controller to switch a P-channel FET in order to achieve the current limit desired. The current limit is measured and set by running the amplified output of a current-sense resistor (R5) back to the VFB pin of the TL3843DR-8 at a level that hits 2.5V when the current limit is reached.

Below is the circuit I've designed.

I've built this circuit physically and it works as a current limiter as expected, except that shortly after the current output reaches the set limit (250mA in this case) and the TL3843 begins to switch and the output voltage begins to drop (with some ripple set by caps C6, C7), the FET (Q2) gets extremely hot to the point of desoldering itself if not outright burning up and destroying itself. One thing I've noticed that while in "current limiting mode" the switching speed is far less that what is set by R8 and C4, approximately 10kHz-20kHz.

Does this have something to do with the switching frequency? Transients on Q2's gate? Something else entirely?

Additionally, let me know if there is a more adequate chip for the job I'm trying to do, or if there is something fundamentally wrong with my design that I've overlooked.

Regards,

Adrian

  • Circuit attached, above link seems broken

  • Hello Adrian,

    Thank you for your interest in the TL3843 PWM controller. 

    It seems to me that your concept should work in principle, but I do believe there is a fundamental design detail that is being overlooked.
    I think you want Q2 to act as a PWM switch where the duty cycle reduces as needed to limit the output current to 0.25A.

    If the load demands more current than the limiter will allow, then the output voltage has to fall. Depending on the nature of the load (constant resistance, constant current, constant power, combination, etc.), Vout can fall a little or a lot.  The SOT-23 package of Q2 is rated for about 0.5W maximum dissipation (depending on the pcb foot-print heating available) and that translates to a 2-V maximum average drop across Q2. And that 2-V drop already puts the junction temperature to its maximum. Any higher V-drop will overheat the device, possibly to the point of destruction.

    To act as a PWM limiter, Q2 must be able to switch on and off at your target 80kHz.  But each on period, assuming full FET saturation, there is no significant impedance between the 24V source and the load, so high peak currents will flow, first to recharge Cout depletion during Q2's off time and then to match what ever the load current is being demanded. At that point when Iout exceeds the 0.25A limit, the loop should shut off Q2.  What you will get are very high peak currents at very narrow duty cycles, so you will have a lot of conduction loss and switching loss in Q2.  

    For this concept to work, I think you need an impedance between Q2 drain and the output caps to limit the drain current. To avoid losses during normal load, it should be a low-R inductance.  This inductance then operates like a buck-derived current source when limiting.  An ultra-fast free-wheeling diode to GND will be needed to supply the inductor current when Q2 is off.

    Aside from that, I don't understand your Q4 biasing.  I think you want a fast inverting stage between the U2 output and the totem-pole buffer, but your arrangement slows Q4 down considerably.  I suggest to reduce R6 to zero-ohm.

    Regards,
    Ulrich

  • Hi,

    Can you probe the Q2 Vds so to know if Q2 is in switch mode by checking Vds when Q2 turn on?

    Can you check if the MOSFET is rated ok for the current?