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TPS24751: Reverse blocking FET

Darren Jenkins
Genius 12551 points
Part Number: TPS24751


Hi eFuse team,

I'm talking with a customer about using the TPS24751 with a reverse blocking FET, like was done in the EVM and in Figure 46 of the datasheet.  They have built a board and are having some unexpected behaviour, and we're trying to get to the root cause. 

On the EVM, the VGS-thresh of the FET selected is 1.0 to 1.8V.  Other than just copying the EVM, do we have a spec for the FET selection in terms of VGS-thresh and any other requirements?

For example, I expect the VGS-thresh of the external FET must be lower than that of the internal FET, so the internal FET is conducting during soft-start and the load is "visible".  

Thanks,
Darren

  • 0
    TI__Guru 57737 points

    HI Darren,

    I hope you already understand the below point,

    • The Blocking FET added in the circuit will only block reverse current when the device is in OFF condition. This is because TPS24751 does not have the intelligence to detect the reverse current and block it by turning OFF the FETs.  

    Hope you are not expecting the blocking FET to block reverse current when the device is ON.

  • 0 in reply to Praveen GD
    TI__Genius 12551 points

    Hi Praveen,

    Yes, I understand that, thanks.

    I was asking more about the gate voltage versus VDS on the external FET. 

    After looking more at this datasheet, there may be something else I'm misunderstanding.  Does the TPS24751 limit the current on ramp by sensing the current, or does it only limit the inrush current when you apply a capacitor/resistor on the GATE pin (ie. just by slowing the gate rise and without feedback)?

    Thanks,

    Darren

  • 0 in reply to Darren Jenkins
    TI__Guru 57737 points

    Hi Darren,

    Normally the startup behavior of the gate is described in datasheet section 9.4.2 as shown below.

    If a RC is added at the gate pin the device will startup as per section 10.2.2.2 in datasheet shown below,