Hi,
Could you please let me know the output condition of PG just after POR?
Just after POR and not rump up to VDD = 0.4V, The device may not run. In this case, will PG output keep LOW? or should it be open?
Regards,
Nagata.
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Hi,
Could you please let me know the output condition of PG just after POR?
Just after POR and not rump up to VDD = 0.4V, The device may not run. In this case, will PG output keep LOW? or should it be open?
Regards,
Nagata.
Excel -san,
Thank you for your support. I understand PG out is High-Z state under UVLO. I would like to know Vout condition in under UVLO in this time. Is is possible to keep 0V in all of voltage under UVLO? Or should it be High-Z when the input voltage is <0.4V?
Regards,
Nagata.
Hello Nagata-san,
I will get back to you on the output discharge behavior under UVLO.
Keep you posted.
Best regards,
Excel