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Here is customer's layout plot and datasheet's recommendation, RD is wondering to know which one is better for layout optimization?
and which one is better on the ripple/noise performance, and what is the reason? Thanks.
Hi Brian,
TI's reference layout is better in comparison with customer's layout. See the details below.
#1. Placing the SW pin trace under the IC is prohibited because it generates high switching pulses that can affect the function of the signals pins of the device when it comes near to it.
#2. In the current layout, the VIN pin is not connected to the input capacitor. How do they intend to connect it? via vias? If that is the case, the output inductor needs to be push downward to create space for the vias which increases the trace parasitic inductance between SW pin and the output inductor (shortest connection as possible is recommended).
Best regards,
Excel
