UCC28780: ucc28780- still no RUN

Ulrich:

Update and correction from an earlier post this morning.

#1  I reported REF & RUN were .5V- incorrect. The probes were x10, so these had correct levels. THAT WAS EXCITING.

Short lived.

#2 Something else went wrong with proto 1(was  rebuilt)  ). SN6505 based bias or something else started interacting with VBULK as soon as VDD, REF, RUN  came up. 

During exploration of root cause, the controller went dead at  REF & VDD pins . I think I know why. Because this proto is varnished, can no longer be fixed.

Got to finally abandon it.

We will have proto 3 & proto 4 ready. 

Given this long struggle, we do need someone familiar in our area(FAE?)  with Debugging per the Document to help in  the lab

Possible?

robin

Hello,

I have assigned this question to an expert on the part. He should be getting back to you shortly.

Hello JAden:

Thanks for picking up the post stream on this topic.

We have been following this debug document for a while.

Issues we encounter are not covered by this document although it is excellent in all respects.

We observed the chip fail with VBULK only 25v! Pins 15(VDD) and 14 (VREF) went short.

Here is my hypothesis: if you run the startup sequence up to 25V VBULK  ( or beyond) repeatedly to explore why RUN is not changing level ( followed by 1st PWML), these pins go low impedance because neither pin can drive the capacitors with the waveforms repetition in 20ms to  50ms. I saw the pins die just doing that.

Can you please verify if this is at all possible?

Since we have not been able to get RUN or PWML so far, we do lose the chip repeatedly. Earlier we suspected ESD or even my probe shorting pins 15 & 14 inadvertently.

But now I am sure the startup process cannot be repeated. Yet, it is hard to get the chip fully functional. Should we add a series resistor to limit currents out of the pins? Such as 100 Ohms? And then once the whole circuit operates, take them out?

If you are interested , here is how we test the circuit(Ulrich has our schematic).

- In an assembly without the controller installed, we inject a 2usec PWM at the lower GAN through the isolator( we have an isolator even for lower GaN). Upper GaN is kept OFF.

Apply VBULK: now you can check the whole power stage: VSWS node, current sense amplitude, ringing, VS at the pin without exceeding startup voltage at VDD, secondary output , rectification by the GaN & UCC 24612 operation. We then reverse the order of GaN OFF states. Test the upper GaN switching behavior- to make sure it is connected with all pads.

Then we install the chip- knowing all is set up correctly.

We still wont get RUN.

Hence it is a big problem.

Any help in this matter will be very much appreciated.

-robn