CCS/UCD3138A: how to give big dead time

Hi,Yitzhak Bolurian:

    Thank you for you reply.

     I want to update the deadtime base on different load . So I try to update deadtime in the pwm interrupt when the duty cycle come from filter output. I find that the deadtime can change which I set if it less than 1us. But change it to big value for example,4us, the DPWM0B duty will not output. why?

I see, you are trying to implement adaptive dead time adjustment.

The amount of (D+ (Period -D) + Dead-TimeA + Dead TimeB) should not exceed the period at any moment.

Also, do not change the dead time in a single step.

Try to go from one value to the other gradually.

By smaller steps and see if it helps.

I have try it which set the deadtime(ded time A) step from 50ns to 500ns. And the amount of (D+ (Period -D) + Dead-TimeA + Dead TimeB) should not exceed the period. But after add some deadtime period,  DPWM0B will not output. And the duty control by filter. I don't know why?

Then i also try another method.   set the register of Dpwm0Regs.DPWMEV3.all  to PWM_OFS + Dpwm0Regs.DPWMFILTERDUTYREAD.bit.FILTER_DUTY + deadtime. It also could not implemet big deadtime.

And i see the datasheet. the register of DPWMCYCADJA is only active when the pwm mode is normal.

Do you mean that even the filter stops outputting the duty cycle?

I'm not sure. when the duty come from filter and the module don't have some fault which turn off pwm, I only guess that it is filter reason.

Also I try to find some register which can give me some information. But I don't find it.

I want to set the dead time bigger to implement the DPWM0B duty decrease smaller. Can you give me some advise?

Yes. I have limit the max duty of 45%. Is it related to the deadtime?

Can you send me your configuration?

#define MAX_PWM_DUTY        ((INT32)(PWM_PERIOD * 0.45)) // Maximum value is 0.50 1150
#define START_PWM_DUTY      ((INT32)(PWM_PERIOD * 0.00)) // Maximum value is 0.50 1150
#define MIN_PWM_DUTY        ((INT32)(PWM_PERIOD * 0.01)) // Maximum value is 0.50 1150

// DPWM0A - VIA
#define DPWM0_EVT1      (PWM_OFS + dt_lead)
#define DPWM0_EVT2      (PWM_OFS + START_PWM_DUTY)
// DPWM0B - SEC_DRIVER1
#define DPWM0_EVT3      (PWM_OFS + START_PWM_DUTY + dt_trail)
#define DPWM0_EVT4      (PWM_OFS)
// DPWM1A - VIB
#define DPWM1_EVT1      (PWM_OFS + PWM_SLAVESYNC + dt_lead)
#define DPWM1_EVT2      (PWM_OFS + PWM_SLAVESYNC + START_PWM_DUTY)
// DPWM1B - SEC_DRIVER2
#define DPWM1_EVT3      (PWM_OFS + PWM_SLAVESYNC + START_PWM_DUTY + dt_trail)
#define DPWM1_EVT4      (PWM_OFS + PWM_SLAVESYNC)

//===================================
 // Configure DPWM-0
 //===================================

 // Control-0
 Dpwm0Regs.DPWMCTRL1.bit.EXT_SYNC_EN       = 0;  //// Enable external synchronization [ 0-Disable ]
 Dpwm0Regs.DPWMCTRL2.bit.SYNC_IN_DIV_RATIO = 0;  //// SYN Freq config.

 Dpwm0Regs.DPWMCTRL0.bit.PWM_EN     = 1;        //// Enable PWM operation, wait for Global En
 Dpwm0Regs.DPWMCTRL0.bit.CLA_EN     = 0;        //// CLA Disabled, using curr limit to chop 
 Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE   = 0;        //// Set mode: 0 - Normal
 Dpwm0Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 0;     //// Master mode
 Dpwm0Regs.DPWMCTRL0.bit.CBC_ADV_CNT_EN   = 0;   //// Adv cnt limit disabled
 Dpwm0Regs.DPWMCTRL0.bit.CBC_PWM_AB_EN    = 0;   //// Current limit disabled for AB outputs
 Dpwm0Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX  = 0;   //// Send PWM-A out the A output
 Dpwm0Regs.DPWMCTRL0.bit.BLANK_A_EN       = 1;   //// Enable Comparator Blanking Window for PWM-B

 // Control-1
 Dpwm0Regs.DPWMCTRL1.bit.HIRES_DIS         = 1;   ////Disable High Resolution logic  
 //Dpwm0Regs.DPWMCTRL1.bit.ALL_PHASE_CLK_ENA = 1;     
 Dpwm0Regs.DPWMCTRL1.bit.CHECK_OVERRIDE    = 1;    ////  
 Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL      = 1;   //// UPdate end of period     
 Dpwm0Regs.DPWMCTRL1.bit.GLOBAL_PERIOD_EN  = 0; ////
 Dpwm0Regs.DPWMSAMPTRIG2.all = PWM_SLAVESYNC;  ////
 //Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; ////

 // Control-2
 Dpwm0Regs.DPWMCTRL2.bit.BLANK_PCM_EN = 1;       //// Enable PCM blanking

 dt_trail = PWM_NS(250);
 dt_lead = PWM_NS(200);

 Dpwm0Regs.DPWMEV1.all  = DPWM0_EVT1;      
 Dpwm0Regs.DPWMEV2.all  = DPWM0_EVT2;   // This has to match 3A EV2 for curr limit to match (readjust at end)   
 Dpwm0Regs.DPWMEV3.all  = DPWM0_EVT3;      
 Dpwm0Regs.DPWMEV4.all  = DPWM0_EVT4;      
 Dpwm0Regs.DPWMPRD.all  = PWM_PERIOD; 

//===================================
 // Configure filter0
 //===================================

copy_coefficients_to_filter(&Filter0Regs, (const FILTER_PMBUS_REGS *)&filter0_pmbus_regs);

 Filter0Regs.FILTERCTRL.bit.OUTPUT_MULT_SEL = 0;  //use KCOMP for scaling.

    Filter0Regs.FILTERCTRL.bit.FILTER_EN = 1;        //enable OK here, because nothing will happen until DPWM and front end are globally enabled

 //Filter0Regs.FILTERCTRL.bit.OUTPUT_SCALE = -2;    // YN_SCALE left shift 2
 Filter0Regs.FILTERCTRL.bit.OUTPUT_SCALE = 0;   // YN_SCALE //???

    Filter0Regs.FILTERCTRL.bit.KI_STALL    = 0;

 //Filter0Regs.FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW = (SLOPE_RATE >> 6) + 200;
 Filter0Regs.FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW = MIN_PWM_DUTY;
 Filter0Regs.FILTEROCLPHI.bit.OUTPUT_CLAMP_HIGH = MAX_PWM_DUTY;

I see that you set:

Dpwm0Regs.DPWMCTRL0.bit.CLA_EN     = 0;        //// CLA Disabled, using curr limit to chop 

This means Dpwm0 is not changing duty cycle based on filter output!

This is a configuration that is suitable only for open loop or for peak-current-mode (PCM)!

Are you operating in PCM or voltage mode? (CLA_EN should be set to 1 in this case)

Also the configuration of LooMux to connect Filter0 to DPWm0 is missing.

What is the value of PWM_OFS? Where is this defined?

I will set the register of Dpwm0Regs.DPWMCTRL0.bit.CLA_EN to 1 in the statemachine. Becase I ask the module for startup open loop first. The module is voltage mode.

PWM_OFS is 400. I'm sorry for miss to show you the define.

Hello,

Thanks for asking this question. Since I don't have your full code, and I just guess.  More likely, the rising edge of DPWM0B is out of period or more than EVT4. 

With CLA_EN =1, the rising edge of DPWM0B is EVT1 + FILTER_OUTPUT + (EVT3-EVT2).  You can check the value of each item.

Thanks,
Sean

Sean:

       Thank you for you reply.

       The switch freq is 100K. The period is 10us. The filter output duty is about 2us. And EVT3 - EVT2 is only 100ns. If i want to set the deadtime(EvT3-EVT2) to 4us, i think it is not out of period. I have pay attention to to the period limit.

       I try to the other method that use the register of DPWMCYCADJA for set the deadtime. when deadtime is above 1us, the DPWM will be lose sometime.

What is EVT4?