• State TI Thinks Resolved
  • Locked Locked
  • Replies 10 replies
  • Answers 5 answers
  • Subscribers 63 subscribers
  • Views 1976 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS53647: Tri-state PWM & protection questions

Yi Dou
Intellectual 545 points
Part Number: TPS53647
Other Parts Discussed in Thread: TPS53681

Hi expert,

I have some questions for it:

1. I didn't see tri-state PWM description in datasheet, can it make PWMx output tri-state? If not, how can it turn off both HS and LS MOSFET in DRMOS?

2. When OVP happens, it is said low-side MOSFET will turn on, is there any possibility of oscillation betwwen inductor and output capacitor, making output voltage swing to negative?

3. For serval protections inside(voltage, current, temp...), what is the typical response time? I can only see ADC inside for PMBus telemetry, I'm afraid that it takes too much time to respond, as the reporting rate is low.

  • 0
    TI__Genius 11095 points

    Hello, 

    1- Yes, this device can tri-state PWMs to turn off both FETs during a fault condition, or disabled state

    2- TPS53647 will latch on the low-side FET. It is possible for LC ringing to cause a brief negative excursion on the output. I've seen some designers place a zener diode on the output voltage in cases where this may damage the load device. 

    3- Output voltage protections are implemented in the analog domain, ~2us max latency. Per-phase cycle by cycle current limit is also in the analog domain. Others are indeed using the onboard ADC. 

  • 0 in reply to Matt Schurmann
    TI__Genius 11095 points

    Just want to add one point, that OVP is the only fault which causes PWMs to latch low. Other faults, and disabled state will cause TPS53647 to tri-state PWMs and simply stop switching. 

  • 0 in reply to Matt Schurmann
    Intellectual 545 points

    Thanks. As you mentioned in no.3 question: "Output voltage protections are implemented in the analog domain, ~2us max latency." I'd like learn that how to define the latency time.

    Is it the duration measured from bench waveforms, e.g. from the moment Vo reached protected threshold, to the moment PWM stops?

    Is there any extra deliberate latency included, for de-glitch(understood as sensing blanking time) or averaging filter? 

  • 0 in reply to Yi Dou
    TI__Genius 11095 points

    This latency is defined for a large and fast step size, the output voltage going above the OVP threshold, to the PWMs tri-stating and VRRDY going low. There is no intentional filtering or deglitch for OVP. However, the comparator overdrive can make it appear slower (like if the output voltage goes to OVP+1mV instead of OVP+50mV, the OVP comparator will be slower to respond). 

  • 0 in reply to Matt Schurmann
    Intellectual 545 points

    Hello, for the no.1 item in your first answer, TPS536xx controller can tri-state PWM to turn off both FETs.

    Forget to check with you, can PWMx pins be actively driven to tri-state voltage level by controller itself? Otherwise, it can only be passive biased, by DRMOS CSD95xxx PWM input.

    In another word, if DRMOS is not powered on(or not soldered) but controller is powered, what is the voltage level of controller PWMs output?

    In my test, it seems that there's a weak pull-down inside controller, it cannot show tri-state PWM by itself, without DRMOS soldered.

  • 0 in reply to Yi Dou
    TI__Genius 11095 points

    TPS53647 will make the PWM pins truly high impedance when both FETs are supposed to be OFF. Then the pin state will just be controlled by leakage. 

    TI's smart powerstage devices have an input resistor divider (100k-1Meg) to bias the pins when the controller is not driving them. TPS53647 does not have a user option to drive PWMs to mid-level, but you can add a resistor divider externally if needed. 

  • 0 in reply to Matt Schurmann
    Intellectual 545 points

    Thanks much for answering.

    Actually in datasheet below(it might be taken from TPS53681 if I remember it correctly), there's a spec about tri-state PWM.

    Do you mean that this value is decided by TI's smart power stage? Not the controller itself?

  • 0 in reply to Yi Dou
    TI__Genius 11095 points

    Good question. Let me check with the IC design team about the 100uA test condition for the tristate voltage next week. Some multiphase controllers only drive PWM pins to the tri-state window, then release them, to avoid the possibility of long on/off times during phase drop/turn on/off due to trace capacitance. 

  • 0 in reply to Matt Schurmann
    Intellectual 545 points

    Thanks for check, besides, 100uA test condition is also hard to understand when testing PWMx H-L transition & PWMx tri-state transition.

    Except the topic we discussed above, about how to access tri-sate with controller itself, also, I'm thinking that how you can control the load current to exact ±100uA.

  • 0 in reply to Yi Dou
    TI__Genius 11095 points

    TPS53681 has an NVM option to force PWMs to the VREF voltage during tri-state. This is where the PWM tri-state voltage of 1.7V nom comes from. 100uA is just the test condition. This means that when TI manufactures the device, we test this NVM option, by putting the PWMs at Tri-state, and sourcing/sinking 100uA from them, and ensure the PWM voltage remains within the 1.6-1.8V spec. However, please note this option is disabled by default, and PWMs are true tri-state unless this option gets changed. It is also not exposed in our GUI. 

    TPS53647 does not have this option.