I noticed that when the IC is in OTG mode and a test load pulls more than the limit set in IOTG, instead of limiting the current, it disables the OTG bit. First OTG_UVP_STAT is asserted and then EN_OTG is reset.
Is this the expected behaviour? Because from the documentation I assumed, that it would limit the output current at the set-point. Is there a configuration flag to make it a constant current source?