BQ76952: Design related queries

Hi Darshil,

Thanks for the kind words.  We hope the BQ76952 will be a valuable and effective component in your designs.

1. The PACK pin might be tied to the top cell (through the 10k suggested).  The LD pin could be tied high, low, or manipulated depending on how you want to use it.  LD has a wake up circuit, if tied high the part will not shut down.  If tied low you can't use it to wake the part.  LD also has a current fault recovery mechanism.  If you manipulate the pin you will need a circuit depending on the desired function.  If you want to wake it it needs to be able to be pulled up sufficiently.  If you want to use it for current recovery you will need to pull it low and release at an appropriate time.

2. Pre-charge and Pre-discharge do not have a low side (logic) output, these will need to be level shifted to the low side if you wish to use them.  You would want to determine how and if to combine the outputs from the 2 parts. If pre-charge is enabled due to low cell voltage instead of charge, the 2 devices would each need to control precharge.  Pre-discharge is enabled to charge a load capacitance before enabling the discharge FET.  If either part could enable the FET last then either part should likely enable pre-discharge last.

3. DCHG and DDSG can only drive logic levels.  Since the highest logic voltage is 5V with tolerance, and a blocking diode is needed for the charge path, FETs with low defined RDSON would be needed.  This is most likely to be suitable only with low current applications when a suitable FET is identified.  Generally you will need a supply and driver to allow use of common FETs.

4. DCHG and DDSG of the upper device can not directly drive CFETFETOFF and DFETOFF of the lower device through a resistor.  Both sets of signals operate with respect to VSS of the connected device and the VSS pins will have some substantial voltage offset between them.  A level shift or isolation circuit will be needed.

5. Yes, ALERT from the upper device could be level shifted to the reference level of the lower device and MCU and combined in logic.  Similarly the RST_SHUT command from a MCU can be level shifted to the different VSS reference for the upper device so that both devices can be controlled.

6. We do not have a document or design reference for stacking the devices at this time.  So far out expectation has been that a MCU would commonly be used in a stacked system to provide status for the battery, a common port for configuration, balancing between the devices, a combined history if desired, and potentially control of recovery.  An MCU could be deopopulated if you determine standalone behavior is suitable.

 7. Yes, we expect the sense resistor could be shared with a gauge, the 2 devices should have separate input filters.

8. Yes, splitting the cell count equally or approximately equally for a stacked design seems a good choice to provide good margin for the regulators for I/O. The top and bottom 2 cells of each device must be used for proper operation. See section 16-6 of the data sheet for tips on connecting unused inputs. There is no specific guidance on whether it is better to connect VC15 through VC10 together vs connecting pairs VC15 to VC14, VC13 to VC12, etc.  Connecting pairs may have benefits in PCB placement or routing.