• State TI Thinks Resolved
  • Locked Locked
  • Replies 12 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 480 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS25947: Reverse current protection

Hirokazu Takahashi
Expert 8420 points
Part Number: TPS25947
Other Parts Discussed in Thread: TPS25942A,

Dear Support team,

I would like to know the reverse current protection with linear ORing.
According to datasheet, VREVTH is defined as 29.5mV@typ.
I guess that BFET will be still turned on and reverse current will flow during Vin-Vout is less than VREVTH=29.5mV.
Is my understanding correct?

Best Regards,
Hirokazu Takahashi

  • 0
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is linearly regulated to maintain a small constant forward drop (VFWD) = 16.8 mV in forward conduction mode and turned off completely to block reverse current if output voltage exceeds the input voltage. This closed loop regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures there's no DC reverse current flow. 

    In case, output voltage exceeds the input voltage very fast, the BFET needs to turn-off very quickly. So, the device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast response (tRCB = 1us) to transient reverse currents. In this interval, transient reverse current will flow till VREVTH reaches 29.5mV and till BFET is turned-OFF.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    TI__Expert 8420 points

    Hello Rakesh-san

    Thanks for your reply.
    I could understand VREVTH will be defined as threshold at less than 1us fast reverse voltage event.
    But I haven't been able to understand why reverse current will be zero at slow reverse voltage event yet.
    Are there any threshold for Vin-Vout at slow reverse voltage event?
    Is reverse current at slow event defined as IREVLKG 0.5uA?

    Best Regards,
    Hirokazu Takahashi

  • 0 in reply to Hirokazu Takahashi
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    As Vout starts to rise over Vin, the current through the path decreases. The device tries to regulate gate of the BFET to maintain 16.8 mV forward voltage but as soon as it fails to regulate, the gate of BFET is turned OFF smoothly.

    The threshold Vin-Vout should be 16.8 mV for slow events. I will double check and confirm.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    TI__Expert 8420 points

    Hello Rakesh-san

    Thanks for your reply.
    I would like to confirm the actual phenomenon with some waveforms.
    I could find any reverse current at the point increasing Vout voltage in Figure 8-15 of datasheet.
    Could you please show more detail vertical scale of IIN, VIN and VOUT?
    And I could find reverse current at fast event in Figure 8-14 of datasheet. Could you please more detail vertical and time scase of IIN, VIN and VOUT at the point of VOUT step?

    Best Regards,
    Hirokazu Takahashi

  • 0 in reply to Hirokazu Takahashi
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    The vertical scale in Figure 8-14 & 8-15 is 5A/div. We have planned to capture better waveforms for RTM release to show the difference in reverse current phenomenon for slowing Vout & fast Vout rising cases.  

    Thanks for pointing this functionality.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    Please let me know if you have any follow-up questions ?

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    TI__Expert 8420 points

    Hello Rakesh-san

    Thanks for your support.
    I have some additional question below.

    Q1. Could you let me confirm the condition selecting fast voltage step and slow voltage ramp.
    When Vout - Vin > Vrevth(29.5mV) will be kept over tRCB (1us), BFET will be turn off as fast voltage step. Is it correct?
    If there will be other condition, please let me know.

    Q2. What different is TPS25947 during slow voltage step from TPS25942A diode mode.

    Q3. Do you have any plan to release TINA TI simulation model of TPS25947? If you will have it, when will it be done?

    Q4. Are there any products supporting DMODE pin fuction except TPS25942?

    Best Regards,
    Hirokazu Takahashi

  • 0 in reply to Hirokazu Takahashi
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    A1) correct.

    A2) When diode mode is enabled in TPS25942A, the BFET is not controlled. Only body diode of BFET provides the path.

    A3) We will be releasing PSpice model (No plan for TINA model as of now) for RTM of TPS25947

    A4) No.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    TI__Expert 8420 points

    Hello Rakesh-san

    Thanks for your support.

    Could you let me confirm the condition for the slow voltage ramp?
    I understand that BFET will be turn off as fast voltage step when Vout - Vin > Vrevth(29.5mV) will be kept over tRCB (1us) according to previous post.
    Will the condition except it go to the slow voltage ramp ?
    If there are any other condition for definition of slow voltage ramp, please let me know.

    Best Regards,
    Hirokazu Takahashi

  • 0 in reply to Hirokazu Takahashi
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    The condition is... As the load current drops, VIN - VOUT Forward regulation voltage drops. The device fails to regulate gate of the BFET to maintain 16.8 mV drop and hence turns-OFF the BFET smoothly.

    Best Regards, Rakesh 

  • 0 in reply to Rakesh
    TI__Expert 8420 points

    Hello Rakesh-san

    Thanks for your support.

    I want to know the condition which the slow ramp will be exchanged with the fast ramp.
    I guess that there may be the timing speed which the BFET regulation can't follow with the slow ramp.
    If BFET regulation can follow 1us as tRCB, I think the reverse current will completely blocked. Is it correct?

    Best Regards,
    Hirokazu Takahashi

  • 0 in reply to Hirokazu Takahashi
    TI__Guru** 105361 points

    Hi Hirokazu-san,

    Correct.

    The regulation loop is slow loop with typical bandwidth in the order of 50kHz. If the fast ramp of Vout causes 29.5mV drop, it acts as large signal to the loop and turns-off the BFET in 1us (typ).

    How fast/ slow ramp is expected in your system ? Is there any concern if small reverse current flows in your system ?

    Can you share application use case, EE details as well.

    Best Regards, Rakesh