TPS3870-Q1: Latch mode(CT=0V) operation

Yusuke Mukuno

Part Number: TPS3870-Q1

Hi expert,

My customer plan to use TPS3870J4080DSERQ1 (0.8V) with latch mode(CT=0V).

They plan to input pulse to CT pin for unlatch.

If they will input over 1.15V voltage continually to CT pin, how does the Reset output work at this timing? (at Sense pin > 0.8V)

In case of the following waveform (datasheet Figure27)

Why will the reset pin be High-Z after unlatch?

I think, The reset output will be low after unlatch, because Sense pin=1.2V (= OV condition).

Thanks

Muk

over 4 years ago

0 Ben C over 4 years ago

TI__Guru 56345 points

Hi Muk,

Yes, if the CT pin receives a voltage that is above 1.15V, the RESET signal will be de-asserted (high state) but it depends on the voltage of SENSE pin. If the SENSE voltage is above 800mV * (+ 0.25% - typ) or (worst case VIT+(OV) = 837.6mV (4.7%)), /RESET will stat asserted even after you apply a voltage greater than 1.15V on the CT pin.

In figure 27, /RESET is at high-z because the sense voltage is not above VIT+(OV) and the application is monitoring a rail voltage of 1.2V.

Ben