• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 63 subscribers
  • Views 702 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5106：

William walker
Prodigy 30 points
Part Number: LM5106

Recently, lm5106 was used to design the half bridge driver of the motor. The driver drives a 600W motor with 500 rpm. When the power is cut off for the whole machine, the upper tube of the board bridge driver is damaged;
After measurement, when the power is off, the upper tube drive is opened wrongly for 20ms. At this time, VDD voltage is 0V, Hb voltage is 10V relative to HS voltage, Ho voltage is more than 6V relative to HS voltage, and VDD, en, in input are all 0V.
When VDD is 0V and Hb voltage is more than 10V relative to HS, Ho has more than 6V output relative to HS.
In this case, why does the driver chip have Ho and why does it have output? What should we do about it?

  • 0
    TI__Mastermind 23215 points

    Hello,

    Thank you for the interest in the LM5106. I have some questions about the application to get more information so we can provide better advice.

    Can you describe the power down sequence? Ex stop PWM drive control signals, power down HV rail, power down bias.

    Can you provide a schematic, partial is OK, of the power devices and the gate drive components?

    It will help to see scope waveforms of the condition you describe. Can you show the drive PWM signal, HO-HS and HB-HS in the conditions you describe?

    I am wondering if there is some power train perturbation which is causing the Vgs to have residual voltage after the driver has lost bias voltage. You can add capacitance on the MOSFET gate to source close to the MOSFET pins which will reduce the Vgs voltage disturbance from the drain to gate miller charge. Can you try adding this capacitance if not in place?

    Regards,

  • 0 in reply to Richard Herring
    Prodigy 30 points

    Hello,

    Thank you for your reply.

    The power-off sequence is: EN pin changes to 0V, VDD changes to 0V after 400ms, and then a driving waveform appears immediately on the upper tube. Observe the rising and falling edge of the waveform is very fast. It is speculated that this waveform is probably not coupled by the parasitic capacitance of MOSFET.

    This is the upper tube drive waveform of half bridge.That 20 ms pulse is an abnormal waveform.

    The waveform of this picture is EN in yellow, HS in blue and HO in purple,The reference points are all VSS.

    This is an enlargement of the previous image.

    Last night, I conducted an experiment. The whole machine was powered off and the VDD voltage was 0V. Only hb-hs was supplied with power. After measurement, ho-hs had a high voltage output of more than 6V. This high voltage output is the root cause of the upper tube damage.

    Regards,

  • 0 in reply to William walker
    TI__Mastermind 23215 points

    Hello William,

    Thank you for the waveforms. It sounds like from your explanation that the unexpected HO pulse happens when you think the VDD for the driver has reached 0V, confirm if that is the case.

    I know you mentioned the EN goes low before the VDD power down, can you confirm if the driver PWM signal stops as well?

    Can you tri something as an experiment, and also review if you require a boot capacitance as high as 10uF?

    Try changing the boot capacitance to 4.7uF, 2.2uF to see if this helps with this behavior. I am thinking if we can get the HB bias below its UVLO threshold before VDD completely discharges it may prevent this unexpected pulse.

    Regards,

  • 0 in reply to Richard Herring
    Prodigy 30 points

    Hello Richard Herring,

    I tested the circuit independently,
    When VDD voltage is 0V, independent power supply is directly used to supply power to hb-hs. When the supply voltage reaches 10V, ho will output high level.


    After testing, there are currently three solutions,
    1. Increase the capacitance of VDD;
    2. Increase the load of hb-hs or decrease the capacitance of hb-hs;
    3. When MCU detects VDD voltage drop,it will reduce motor speed quickly to prevent damage caused by high back EMF and protect MOSFET.


    Thank you again for your reply!

    Regards,

  • 0 in reply to William walker
    TI__Mastermind 23215 points

    Hello William,

    I am glad you found a workable solution to your concerns with the LM5106. Let us know if we can assist with any questions in the future.

    Regards,