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TPS3430: watchdog timeout

FRANK1
Expert 8535 points
Part Number: TPS3430

Hi team,

A customer have concerns on our product of TPS3430 .

TPS3430 has a typical watchdog timeout period of 1.6s.
Just I am curious about the range specified for Time out as 1.0s~2.25s,

why there is minimum, maximum range specified.
What exactly happens if the reset pulse occurs between 1.0s-1.5s and 1.7s - 2.25s?
Kindly clarify the doubts in details.

Thanks.

  • 0
    TI__Guru 56345 points

    Hi Frank,

    Just to be clear, you are looking for a timeout range from 1s to 2.25s, correct?  If you set both SET0 and SET1 to "High", you will get a window time-out time between 800ms to 1600ms.  Is the 1600ms you are referring to the typical watchdog timeout period of 1.6s?

    The min and max range is specified because the calculations are based on ideal capacitors.  See below:

    The picture below details what happens if a WDI pulse occurs outside the watchdog window:

    Ben

  • 0 in reply to Ben C
    TI__Expert 8535 points

    Hi Ben,

    Thank you for your response.

    TPS3430 has a typical watchdog reset delay of 200ms.
    Just I am curious about the range specified for Time out as 170ms~230ms, why there is minimum, maximum range specified?
    What exactly happens if the reset pulse occurs between 170ms-199ms and 201ms – 230ms?
    Kindly clarify the doubts in detail.

    Thanks.

  • 0 in reply to FRANK1
    TI__Guru 56345 points

    Hi Frank,

    There are min and max limits because of tolerances when manufacturing silicon, over temperature, VDD input range, and etc. 

    There might be some confusion on your end regarding the limits.  Typically, you will get 200ms of delay but at one extreme end of the temp or voltage range and/or process variation, the output delay may not be at a typical 200ms.  With the min and max spec range, TI guarantees that the 3430 will have an output delay time between 170ms - 230ms over temp, VDD, and process.  

    I hope this clarifies any confusion that you may have on the reset delay time spec.

    Ben