UC1846-EP: Power-on Issues with UC1846-ep

Hi,

Can you provide your schematics for review? Your presentation says OUTA and OUTB present high before Vref > 400mV, we need to see your schematics to understand what else needed to add in.

Hi Silvia,

Thanks for sending the detailed waveforms in your attached pdf report. A few comments:

1. Slide 5: I don't think the AOUT terminating is related to the VREF. I believe it is correct that there is no internal UVLO for VREF
2. Slide 5: Takes about 40 us for VREF to reach ~5V with 300 nF, I=c*dV/dt=37mA>21mA but at VC~8V (UVLO On), VREF~400 mV. Both outputs should be held OFF until the IC is smart. Do you have pull down resistors on Q1, Q3 - something like 10 kΩ from gate to source (GND)?
3. 5VREF rise is very slow - can the 916 kΩ be scaled down and see if 5VREF start up increases?
4. 100 nF on VC (VIN) is good for bypass (noise) but I advise you also have a few uF in parallel. Maybe stack on top of the 100 nF as an experiment

Regards,

Steve M

Hello Steve,

Thanks a lot

1. Slide 5: I don't think the AOUT terminating is related to the VREF. I believe it is correct that there is no internal UVLO for VREF                                     -->    agreed. Assumption was that since the VCC starts rapidly, the UVLO has been deactivated, but since the internal logic is supplied with 5V1, the outputs are not defined thus yealding undesired behavior on the outputs. Additional reason for this assumption is that both outA and outB are “1” which should not be the case due to the toggle flipflop. Nonetheless, this is discarded when the VSS slew rate is reduces, the pulse width increased.
2. Slide 5: Takes about 40 us for VREF to reach ~5V with 300 nF, I=c*dV/dt=37mA>21mA but at VC~8V (UVLO On), VREF~400 mV. Both outputs should be held OFF until the IC is smart. Do you have pull down resistors on Q1, Q3 - something like 10 kΩ from gate to source (GND)?                        ---> 10k pull down has been added and no modification has been observed.
3. 5VREF rise is very slow - can the 916 kΩ be scaled down and see if 5VREF start up increases?                                                                                         --> I don’t understand the suggestion. The SR of the 5V1 is defined by the 300nF capas and current limit of the VREF (>21mA). The static consumption on 5V1 is aprox 10mA. I can check if one of the three 100nF can be removed, resulting in rise time reduction to 27us. The same configuration has been used with uc1825-sp and no issued have been observed
4. 100 nF on VC (VIN) is good for bypass (noise) but I advise you also have a few uF in parallel. Maybe stack on top of the 100 nF as an experiment        --> there is 20uF behind the darlington switch (slide4, q1806/07) on the node PEIM_VCC_12V. nonetheless, cap increase to 470nF has been tried with no improvement. Since 20uF is dominant capacitor, the VCC SR remains unaffected by the VCC capas. Moreover, the issue is observed during the power on and not in the steady state (once the prim is recovered after the shoot through caused by the PWM, the whole converter has expected behavior).

Additional comment related to the waveforms on the slide 7: it lloks realy strange how the CT and SS pin behaves during the poweron: while the outputs are high, both signals increase up to around 1V and both of them have capas (CT 1n+50Ofm and SS just 1n)

We really appreciate your support.

Thanks

Hi,

The affected schematic is in page 4 of the presentation

Dear Hong Huang,

Thanks a lot. This seems to solve the issue. However, we think it could be sensitive to failure. We are doing more investigation. In the meantime, before we can give more detail to ask for your support, if you can, we would like to know if UC1846-EP could be supplied with Vin=15V & VCC=0V without restrictions (permanentely).

We are really thank you to TI for the support provided in this technical issues, not only related with the part

Thanks but that is not the goal.

we are investigating the posibility to turn-off the device in this configuration (VIN=12V and VCC=0V) but we are not sure that this supplying condition does not stress the device.

thanks

Dear Hong Huang,

Yes, but we think there could be a failure mode where the shutdown will not be responding, so we were thinking in the other possibility (vcc=0). As it is not recommended, we are studying the design a little further. Shall we close this thread, and in case of further support reopen it?

Thanks