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UCC25705: UCC25705 Switching Frequency

chingyu Wang
Prodigy 140 points
Part Number: UCC25705

Hi, Ti member 

I want to operate 100kHz and the maximum duty close to 99% by UCC25705.

have some questions about PWM IC design:

.

  • the block diagram shows : this mode 0 , the timing of capacitor is discharge through low impedance directly to ground.  (Is impendence 80 ohm?)

    the timing of turn-off is the same at different Vff?    (close to 75ns)

  • what is limitation for discharge current of timing capacitor ? 
  • Can the UCC25705  operate at 1% PWM to limit power delivery ?   the customer need soft-start and output current limit function (larger current but small voltage

thank you

  • 0
    TI__Expert 7395 points

    Chingyu,

    Thanks for the inquiry here. I hope you're doing well.

    The team supporting this IC is in the US and presently on holiday. Please expect a response by end of the day Tuesday next week US time. 

    Regards,

    John

  • 0 in reply to John Stevens
    TI__Mastermind 32975 points

    Hi Chingyu,

    During MODE 0, the internal CT current sink (and VFF current source) is bypassed and the CT capacitor is discharged directly to GND through an internal impedance of 80 Ω. For MODE 0, the internal VFF current source is also disabled and this means the turn-off time is fixed at ~75 ns. Also because the VFF current source is disabled and VFF is set by an external resistor divider, there is no duty cycle clamp in MODE 0. The limitation for CT discharge current is current sink capability when operating in MODE 1 (250 uA) and I=V/R rating when operating in MODE 0, where V is the CT RAMP voltage and R=80 Ω. Please also e aware that UCC25705 has no OUT drive capability. The OUT signal is intended to be the input to a gate driver IC. Even when a high performance gate driver is used, I don't think 1% duty cycle is achievable due to the slow edge rates (rise/fall time) and MOSFET delay. External soft-start is easy enough to design. Current limiting is not easy to implement with VMC. The UCC25705 ILIM pin is for OCP only. CMC gives true cycle by cycle current limit.

    Regards,

    Steve M

  • 0 in reply to Steven Mappus1
    Prodigy 140 points

    Hi, Steve 

    Thank you for detail explain. 

     I don't think 1% duty cycle is achievable due to the slow edge rates (rise/fall time) and MOSFET delay.

    I want to know this control IC can control pulse width of signal below 1% at 100kHz without other facts.

    Current limiting is not easy to implement with VMC:

    if I design the BW of current limit loop among 10Hz ~ 30Hz , is easy to implement ? 

    I don't care the output ripple and dynamic at current limit condition.

    My case  :

    Approximately 100% PWM buck converter , the system allows PWM fully on at some conditions.

    CMC is better than VMC to control over power or current , but the slop compensated at 97% PWM is more difficult to design and trend to VMC characteristic. 

    has any ideal about that? 

    thank you

  • 0 in reply to chingyu Wang
    TI__Mastermind 32975 points

    Hi Chingyu,

    I want to know this control IC can control pulse width of signal below 1% at 100kHz without other facts.

    ANS: No

    CMC is better than VMC to control over power or current , but the slope compensated at 97% PWM is more difficult to design and trend to VMC characteristic. has any ideal about that? 

    ANS: No, at 97% duty you will need so much slope comp the CMC will appears as VMC.

    Regards,

    Steve M