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TPS40305: Device failed in the 200MHz-1GHz FCC EMI Testing

Part Number: TPS40305

Our product is failing in the 200MHz-1GHz FCC EMI Testing. 

After the debugging we have identified that we TPS40305 is generating that noise specifically Q7 & Q8.

Kindly find the result of EMI test.

Kindly find the layout screenshot.

By changing the value R789 & R790 from 0R to 10R we are seeing the improvement but not that much.

Let us know further steps to resolve the issue.

  • We are also getting the 215MHz to 250MHz random peak along with 433MHz peak.


    My apologies for the delay in getting back to you on this.  Thursday November 26th and Friday November 27th were holidays here in the US.

    The 215MHz and 250MHz noise is most likely L-C tank ringing from the parasitic inductance of the bypassing of the drain of Q7 (high-side FET) to the source of Q8 (low-side FET) and the parasitic capacitance at the switching node (Source of Q7 and Drain of Q8) 

    The 450MHz noise is likely related to the rising and calling edge rates on the switching node.

    Unfortunately, the existing layout does not appear to have provisions for the components that are typically used to help suppress this type of noise. 

    Without changing the layout:

    Change C101 from 10uF to an 0402 size 10nF capacitor.  The small package 10nF capacitor will offer better bypassing effectiveness with lower parasitic inductance than the 10uF capacitor.

    You can counter the loss of input bypassing capacitance by changing C590 from 10uF to 22uF, which will also help split up the resonant frequencies of the input capacitors, and help reduce the resonant peaking.

    Change R789 (low-side FET gate resistor) and R790 (high-side gate resistor) so the rising edge and the falling edge have different edge rates to help reduce the peak energy of the noise.  a 3:1 ratio usually works well, such as a 3.3-ohm  for R789 and a 10-ohm for 790.

    If you can make changes:

    Adding an R-C snubber from the drain of Q8 (SW node) to its source (GND) with approximately 1nF of capacitance and about 1-ohm resistance would help dampen the ringing.  Ideally, this snubber would be located between Q7 and Q8.

    Adding Vias to the VIN and GND pads as close to Q7 and Q8 as design rules allow would allow additional parallel input capacitance to be added on the backside of the PCB to further reduce parasitic input inductance would also help.

    Adding a resistor between C86 and the BOOT pin would allow the rising and falling edge of the switching node, splitting up the high-side gate drive resistance into separate components to better tailor the rising and falling noise.  Setting each to 3.3-ohms so there is 6.6-ohms of  series resistance during turn-on, and 3.3-ohms of series resistance during turn-off generally works well, though other combinations are possible.


    Please let me know when you have had a chance to try the recommendations above.